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DP83867 video application

Jacky Chen29
Genius 4735 points

Other Parts Discussed in Thread: DP83867IR, DP83867CR

Hola,

I have some questions about DP83867 video application as below：

1. What's the range of the termination resistor for RGMII？

2. What's the input impedance of the RGMII TXD[3:0]、RGMII GTX_CLK？

3. What's the output impedance of the RGMII RXD[3:0]、RGMII RX_CLK？

For above questions are for PCB layout concern(crosstalk issue).

Below question is for programming issue：

After reset, we can adjust the resistor ratio to set operation mode, after that does MDIO's command can cover resistor's setting？

  • 0
    Genius 4735 points

    Hola,

    Please somebody help to reply my questions. Thanks ～

  • 0
    Genius 4735 points
    Hola,
    Can someone help to reply these questions？Many thanks ～
  • 0
    Genius 4735 points
    Does TI have any expert of DP83867 can reply these questions？！

    These questions were pending for a few weeks！We need to fix these issue for urgent case due to its under schematic drawing or it will be changed solution..
  • 0 in reply to Jacky Chen29
    TI__Mastermind 19780 points

    Hi Jacky,

    RGMII & GMII signal pin output/input impedance is adjustable between ~50 Ω to 105 Ω

    The default value is ~68 Ω

    Adjustment of the impedance is done with register 0x0170, listed in the datasheet.  It is a single setting that applies to all MAC pins.

    Bits [4:0] = 0x00 corresponds to ~105 Ω

    Bits[4:0] = 0x1F corresponds to ~50 Ω

    Yes, all strap options (resistor ratio optional settings) can be changed via MDIO after boot-up with the exception of the PHY address.  How you change them depends on the function.  For example, mirror mode can be enabled by strap or by MDIO using the "Port Mirror Enable" bit in the CFG4 register (address 0x0031).

     

    Best Regards,

  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    This is great and thank you very much.

  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    Can help confirm below items description whether it has any problem？Thank you very so much.

    1. The terminal resistor that we will place it as DNP and according to the description that we can turn on the FPGA PAD's inherent resistance(input 25/50/75 ohm、output 50 ohm) and it will get the best response by trace of length 6mil、interval 12mil.

    2. PHY address = 0；we connected all of LED to the ground and if the current low as define value and it will assumed mode 0.

    3. Reset/XI are setting by FPGA, if we not set the basic function by MDIO and we can set the basic parameter after reset by FPGA I/O (mode 3/0).

    4. Below connection whether it has problem？PHY's output A/B/C/D connect to G/B/O/C. (Coffee C / Blue B / Orange O / Green G；trace of length 5mil、interval 5mil)

     


     


     


     

     

  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    Can help confirm below items description whether it has any problem？Thank you very so much.

    1. The terminal resistor that we will place it as DNP and according to the description that we can turn on the FPGA PAD's inherent resistance(input 25/50/75 ohm、output 50 ohm) and it will get the best response by trace of length 6mil、interval 12mil.

    2. PHY address = 0；we connected all of LED to the ground and if the current low as define value and it will assumed mode 0.

    3. Reset/XI are setting by FPGA, if we not set the basic function by MDIO and we can set the basic parameter after reset by FPGA I/O (mode 3/0).

    4. Below connection whether it has problem？PHY's output A/B/C/D connect to G/B/O/C. (Coffee C / Blue B / Orange O / Green G；trace of length 5mil、interval 5mil)

     


     


     


     

     

  • 0 in reply to Jacky Chen29
    Genius 4735 points
    Hola,
    Is there any update, it's been for a few weeks..
  • 0 in reply to Jacky Chen29
    TI__Mastermind 19780 points
    Hi Jacky,

    1. Yes you can DNP the termination resistor and choose the 50 ohm input/output impedance for your FPGA.
    Does the trace length refer to the width? You will have to do the calculations for the trace impedance to match 50 ohm single-ended.

    2. It is not recommended to connect the pins directly to ground, if that is what you mean. For LEDs, follow figure 18 in the datasheet for mode 1(0).

    3. Yes, after reset by FPGA, all strap modes will be resampled. You can set the parameters by MDIO after a reset as well. PHY address can NOT be set by MDIO.

    4. From the schematic I see PHY output channel A connected to Green, channel B connected to Orange, channel C connected to Blue, channel D connected to Coffee. This is the correct pinout.

    Are you seeing a problem with a board or is this in the schematic phase?

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    This is very kind of you. Thank you for your reply.

    We are finished schematic phase and it's under layout phase.

  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    About question 2 that I want to confirm with you as below：

    1. Let SPEED_SEL = 0、PHY_ADD[3:0] = 0.

    2. DP83867IR/CR(48pin)：Quote Figure 22.(Strap Circuit = 0) & Figure 23. & Table 5.(4-Level Strap Pins), and we got SPEED_SEL = 0、PHY_ADD[3:0] = 0.

    3. After reset and it can support 10/100/1000, and MIDO(PHY) address = 0.

    About Figure 18. --> I think it unable to establish because of it only has RGMII interface with 48pin and has no CRS/COL..

  • 0 in reply to Jacky Chen29
    Genius 4735 points
    Hola Rob,
    Do you have any update？Thank you.
  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    About question 2 that I want to confirm with you as below：

    1. Let SPEED_SEL = 0、PHY_ADD[3:0] = 0.

    2. DP83867IR/CR(48pin)：Quote Figure 22.(Strap Circuit = 0) & Figure 23. & Table 5.(4-Level Strap Pins), and we got SPEED_SEL = 0、PHY_ADD[3:0] = 0.

    3. After reset and it can support 10/100/1000, and MIDO(PHY) address = 0.

    About Figure 18. --> I think it unable to establish because of it only has RGMII interface with 48pin and has no CRS/COL..

  • 0 in reply to Rob Rodrigues
    Genius 4735 points

    Hola Rob,

    Can help reply my another concern？Thank you ～

  • 0
    Genius 4735 points

    Can someone help to reply this questions ? Thanks.

  • 0 in reply to Jacky Chen29
    TI__Mastermind 19780 points
    Hi Jacky,

    Sorry for the delay. The email alerts for thread updates aren't doing well.

    Correct, table 6 applies only to DP83867IR. DP83867IR has SPEED_SEL0 and SPEED_SEL1 bits.

    Table 7 applies to DP83867CR. DP83867CR only has SPEED_SEL bit on pin.

    You are correct to interpret the straps in the way you have

    Figure 18 applies only to DP83867IR. Only that device supports MII mode and has CRS pin. In the beginning of MII section, it says MII is only available for PAP(DP83867IR) devices.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Genius 4735 points
    Hola Rob,
    Thank you for your reply.
  • 0 in reply to Jacky Chen29
    TI__Mastermind 19780 points
    Hi Jacky,

    Thank you for your questions. For any further questions, please start a new thread so it gets noticed!

    Best Regards,