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DP83620 - CLK_OUT X1 reference clock pass-through

Greg
Expert 2031 points
Other Parts Discussed in Thread: DP83620

I am planning on using either a 25 MHz crystal or oscillator in RMII Master Mode.  I need a 50 MHz clock output for the MAC of the microcontroller, 25 MHz or 50 MHz for an FPGA's clock, and 25 MHz for the microncontroller's main clock.  From other posts I've read in the forum, it looks like the DP83620 will do what I want.  But I would like someone to confirm that it will and there won't be any issues.  It is my understanding that TX_CLK and RX_CLK will both output 50 MHz, which will work well for the FPGA and MAC.  The data sheet shows the following info for CLK_OUT.

I didn't find any more information on the 25 MHz pass-through option in the data sheet, but from what I read in the forum it appears this is the default mode.  Is that true?  What happens to all three clocks when the RESET_N pin in pulled low, or any software resets are performed?

Thanks,

Greg

  • 0
    TI__Mastermind 19780 points
    Hi Greg,

    Yes, for RMII master mode, the default behavior of CLK_OUT is 25MHz pass-through.

    When RESET_N is asserted, all three pins provide 25MHz until the strap pins are resampled or the DP83620 is placed back in RMII master mode via MDIO access.

    Reset by BMCR register doesn't affect the clocks.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Expert 2031 points
    Hi Rob,

    Thanks. Does CLK_OUT experience any glitches when RESET_N is asserted? I was hoping to use it as the source for the microcontroller's clock. I was thinking I would connect a GPIO of the microcontroller to RESET_N in order to give it a hard reset. But if using the GPIO to assert RESET_N affects CLK_OUT, then that wouldn't be good because it would upset the microcontroller. Maybe there is no need for the microcontroller to give it a hard reset, in which case it a soft reset is all that is needed.

    Thanks,

    Greg
  • 0 in reply to Greg
    TI__Mastermind 19780 points
    Greg,

    We haven't validated glitch free operation of the clock output during RESET.

    I would still give some component of the system the ability to hit the RESET pin if necessary, but it would be in rare cases.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Expert 2031 points
    Hi Rob,

    Thanks for the advice about the RESET pin. I will connect a microcontroller GPIO pin to it just in case.

    It doesn't sound like I will be able to use CLK_OUT to drive the microcontroller main clock. That's unfortunate. I was hoping one crystal could be used for the entire circuit. Is CLK_OUT driven directly from the X1 pin? Even though it hasn't been validated, it seems it would be known what the oscillator circuit does when the RESET line is pulled low. The PHY's clock is a pretty important signal, so there must be some predetermined reaction to RESET.

    Best Regards,

    Greg
  • 0 in reply to Greg
    Expert 2031 points
    Hi Rob,

    I forgot to ask about jitter. I would like to drive an FPGA with one of the clock outputs. The FPGA has a PLL, so I can use either 25 MHz or 50 MHz to get whatever frequency I need. The PLL in the FPGA has limitations on the amount of jitter in the clock signal. I looked through the data sheet for the DP83620 but I didn't see any specs for the jitter on the output clocks. Of course the jitter on the input to the PHY matters a lot, but I was hoping to see a spec for how much jitter the PHY adds to the clock signals. I suspect the jitter on the 25 MHz clock would be less than the 50 MHz clock, since the 50 MHz clock is the output of a PLL, and the 25 MHz clock is the output of the crystal oscillator. If an oscillator is used instead of a crystal, I assume the jitter would be the combination of the external oscillator's jitter and any jitter the buffer in the PHY adds.

    Best Regards,

    Greg