• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 787 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interfacing A VML Output Part to a CML Input

Matt Gould
Prodigy 40 points
Other Parts Discussed in Thread: SN65LVCP40

Greetings All,


I am interfacing a SN65LVCP40 to Xilinix Virtex 5 FPGA.  The Virtex 5 has CML inputs, but the LVCP40 has VML outputs.  Do I need to worry about this?  According to this document:  http://focus.ti.com/lit/an/slla120/slla120.pdf, The voltage levels are slightly different, but the document makes it look like you might be able to change the termination voltage to achieve this.  Has anyone attempted this and if so did it work?  Would it be safer to find a level shifting part to go from VML to SCML?  I'm relatively new to HS design so any help or pointers would be appreciated.

 

Thanks,
Matt 

  • 0
    TI__Intellectual 1360 points

    Matt

    Are you AC coupling the SN65LVCP40 to Xilinx FPGA or DC coupling?

  • 0 in reply to Ajinder Singh
    Prodigy 40 points

    It is AC coupled.

  • 0 in reply to Matt Gould
    TI__Intellectual 1360 points

    Matt

     

    I dont see an issue if you are AC coupled.

  • 0 in reply to Ajinder Singh
    TI__Mastermind 33030 points

    Matt,

    Generally speaking interfacing any of these signal types comes down to a couple of steps.  The parameters that need to be examined are VOD, VOH, VOL, and VCM of both the Driver and Receiver as well as any special termination requirements for the particular logic types.  When you AC couple the signal, the VCM of the Driver is removed and needs to be re-established on the receiver side of the AC coupling caps.  If the VOD of your signal is compatible with the VID of the receiver then all we have to do is terminate to the common mode of the receiver.  Most IC's today have internal termination as well as voltage dividers used to set the common mode of the signal.  Check the FPGA datasheet to determine if there is any internal input termination you should be done (as I suspect is the case).  If there is not any termination or common mode level setting then you will need to provide that externally.  If this is the case you will need to terminate both the positive and negative signals with 50 ohms to a voltage node that is the same as a valid common mode voltage of the receiver, or use two several kilo ohm resistors to create a voltage divider to create the common mode voltage needed.  Furthermore, if the VOD is too large for the receiver's VID, then series resistors can be placed in series on each line to attenuate the signal to a manageable level.

    Jon

  • 0 in reply to Jonathan Nerger
    Prodigy 40 points

    Thanks Jon.  After reading your reply and then re-reading the app note that makes alot of sense.  I have confirmed that the xilinix termination does work the way you suggested.


    Thanks for all the replies, you guys rock.

    -Matt