• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 1862 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

I2C Clock arbitration

namasivayam g
Prodigy 130 points


HI,

    if more than one master is connected on same I2C bus and configured with different clock speed how it works at that time.please explain

Regards,

siva

  • 0
    TI__Genius 16510 points

    Hello Siva,

    The way multi master arbitration works, is that when a master is transmitting a signal, any device transmitting a low while a high is being transmitted by another master will have a higher priority.

    For example, since I2C is an open drain interface, this means that a device can only pull the bus to ground, but to cannot pull the bus high. Instead, it 'releases' the line (you can think of a switch internally that shorts the bus to ground is used to transmit a 0), and a pull-up resistor on the bus is able to pull the line high. In short, this means that if one device is "transmitting" a high (by not pulling it low and letting the pull-up resistor keep the voltage high), and another device transmits a 0, the bus will get pulled to 0.

    Because of this, multi-master arbitration looks for data on the line to be different than what it expects to determine if it has won or lost arbitration.

    Let's use the example where two masters communicate at the same time. First bit is a 0 for both. For the second bit, master A transmits a 0 and master B "transmits" a 1 (releases the bus). Master B will see that the voltage on the bus is not high like it expects, and assumes that another master has won arbitration, therefor it will stop transmitting immediately and let Master A continue.

  • 0 in reply to Jonathan Valdez
    Prodigy 130 points

    Hi,

     Thanks for your reply. But my question is when two master  trying to transfer the data at same time and different clock rate.assume one is 100khz and another ia 400khz.which clock will be in  sclk  bus  line  till any one  get wins?

  • 0 in reply to namasivayam g
    TI__Guru*** 125430 points
    This is discussed at length in the freely available I2C specification. It is the topic of Section 3.1.8 "Arbitration".
  • 0 in reply to namasivayam g
    TI__Genius 16510 points
    Siva,

    As Brad mentioned, this is discussed in the I2C spec.

    In regards to your specific question about different clock speeds, theoretically the slower clock would always win (if they both start at the same time) because the slower clock would hold the bus low longer. So when the faster master released the bus, it would expect to see the bus voltage raise, but it will see the voltage remain low as a result of the slower master, and then it will stop communications.