Hi,
I am using the HPD VD5200 camera that has a FPD Link III output from a DS90UB913Q serializer.
From what I have read, the DS90UB913Q must be used with a DS90UB914Q deserializer.
I purchased a DS90EB914A-CXEVM deserializer EVB and it arrived today. Here was my plan. To take the LVCNOS output from the EVB and go to a breakout board where I swap the signals and run a FPC ribbon cable into our i.MX6 development board. I have some concerns with that.
1) The deserializer EVB can output either 1.8V or 3.3V and our i.MX6 development board indicates it is a 2.5V bus. I can’t find enough information on the I.MX side to determine if that will work, The deserialzer is 1.8v or 3.3v only - is that correct?
This is one IMX development board we have:
https://boundarydevices.com/product/sabre-lite-imx6-sbc/
This is the other:
https://boundarydevices.com/product/nitrogen6x-board-imx6-arm-cortex-a9-sbc/
The Nitrogen board seems newer and better supported, so I was going with that one, however both dev boards use the same BSP and seem to be identical where the camera circuitry is concerned. I know this is not a TI issue - just wondering if you have cone across this before or have any good suggetsions?
2) I saw in a tech note on a completely different chip set that MIPI CPI is limited to VGA resolution (640x480) at 15 fps. That is not going to be enough. However, it doesn’t make sense to me that a 720p camera would be designed with interface hardware that so severely limits output. I cannot find a maximum spec on CPI. Looks like form reading the datasheets I effectively can have a pixel clock of up to 100MHz wich is approximately 100fps at my 720x1280 resolution - is that correct?
3) I also have concern on all the interconnects I need to do. I don’t know if I am going to run into either signal length mismatch problems or noise from where the pins get remapped. I have attached a picture of my mockup.
The two big issue I see will probably be signal reflections, particularly on the clock and crosstalk.
- There are no series resistor terminators on the eval board so we can pretty much guarantee there will be a reflection on the lines which will probably mess up the clock signal. To try and fix this I can either add a series terminator at the source – at J1. or also try a small capacitor to ground again at the source(thinking 10pF or something similar) – this will slow the edge down and will help prevent a reflection.
- To help reduce cross talk I'll make sure there is a ground signal between each signal in your cable. J1 has the same number of grounds as signals – not sure what the connector on the IMX.6 has yet
- I'll keep the cables as short as possible.
Has anyone come across the same issues I have and any nice solutions to make this work?
Below is a picture of my intended setup