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DS125DF410 channel select register (Reg_0xFF)

Casey Morrison
Intellectual 1985 points
Other Parts Discussed in Thread: DS125DF410

Posted on behalf of another E2E user:

Questions regarding the DS125DF410 channel select register, Reg_0xFF:

  1. Does "set" bit 3 of register 0xFF mean "set it to 1"?
  2. In order to reduce the number of I2C (SMBus) writes, can we implement "Write to all channels / Read from channel 0" by setting Reg_0xFF=0x0C?
  3. Is there any sequence required for setting the channel select register (Reg_0xFF)? In other words, must I first select a channel, and then enable broadcast mode, or vice versa, or the sequence doesn't matter?
  • 0
    TI__Intellectual 1985 points

    Answers:

    1. Does "set" bit 3 of register 0xFF mean "set it to 1"?

      Yes, it means set it to 1.

    2. In order to reduce the number of I2C (SMBus) writes, can we implement "Write to all channels / Read from channel 0" by setting Reg_0xFF=0x0C?

      Yes, setting Reg_0xFF=0x0C will cause all writes to be broadcast to all channels, and all reads will be sourced from channel 0.

    3. Is there any sequence required for setting the channel select register (Reg_0xFF)? In other words, must I first select a channel, and then enable broadcast mode, or vice versa, or the sequence doesn't matter?

      No, there is no sequence required. As soon as you write 0x0C to register 0xFF, then you are writing to all channels and reading from channel 0.