• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 34 subscribers
  • Views 755 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMH1983 used for locking to an IEEE1588 derived HSync

William Black
Prodigy 30 points
Other Parts Discussed in Thread: LMH1983

Hi all ,

On my board I have a LMH1983 for normal SDI video locking. I'm using the default loop filter from the data sheet.

I now want to reuse this board to lock to an HSync which is derived from an IEEE1588 clock. This Hsync is filtered but still makes steps of +/- 6ns since the clock which generates this pulse is using 156.25MHz as a base clock. For this I'm not using the VSync or FSync pulses, just HSync. Therefore I'm not relying on TOF pulses, just using the 148.5MHz 

When doing this, the PLL1 never locks. PLL2 and PLL3 are indicating lock. I disabled crash-locking. My question is, Is the 6ns jitter on the HSync pulse to high for PLL1 to remain in lock? This is less then a 27Mhz clock period.

As a fallback scenario I had the I2C interface in mind to control the DAC immediately but these steps are not accurate enough to remain within SDI jitter spec. Correct or am I missing something?

William

  • 0
    TI__Intellectual 1985 points

    Hi William,

    Thank you for submitting your question. Our LMH product experts are out of the office on holiday right now, returning the first week of January, so hopefully we can get you an answer shortly.

    Regards,

    Casey

  • 0 in reply to Casey Morrison
    TI__Guru* 93670 points
    Greetings William,

    Thanks for sending us these questions.

    1). In your setup PLL1 never locks meanwhile PLL2/3/4 are genlocked to PLL1(which is free running using external VCXO). So this is why you see PLL1 not locking while other PLLs are locked.

    2). PLL1 does not lock since HSYNC frequency is out of it's range. Please note table 2 phase detector frequency and auto format detection codes. As you can see, HSYNC clock is in the range of 6 to 67KHz.

    Would it be possible for your FPGA to generate one of these HSYNC clocks - 6 to 67KHz range - noted in table 2 ? FPGA generated HSYNC clocks should be genlocked to 156.25MHz clock. For PLL1 to lock, HSYNC must be one of the formats in table 2 or there could be a custom format but even in this case HSYNC is in order of KHz.

    If possible it would be a good idea if we can get a block diagram of your clocking architecture to support 1588 environment. Perhaps we may have further comments on this.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 30 points

    Hi Nasser,

    Thanks for your reply,

    Just to clarify,

    The process I generate the HSync in is running on a 156.25MHz clock. The HSync frequency it self is a line frequncy for 1080i50. This is within the 6-67Khz range.
     only the steps to adjust this HSync is calculated in the 156.25MHz clock domain. This results in adjusting steps of 6.4ns.

    My peak to peak jitter is worst case 6.4ns.

    Other info regarding the clock architecture will folow later.

    William

  • 0 in reply to William Black
    TI__Guru* 93670 points
    Hi William,

    1). I think 6.4ns of jitter should not be the root cause of PLL1 not locking. Is it possible to disable auto format detection and force 1080i50 format? You can do this using registers 0x05 and 0x20.
    Under this condition, AFD disable, does PLL1 locks? If PLL1 locks this means AFD is preventing PLL1 to lock. On the other hand, if PLL1 is not locking this means there is something about HSYNC pulse that is preventing the device to achieve lock.

    2). Also, please make sure HSYNC frequency is within +/-100PPM. This is the detection range.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 30 points

    Hi nasser,

    Took me some time, but after I had changed the Loop Filter, the LMH is now locking to the recovered H_Sync.

    PLL1 remains in lock with lock with all default settings for the applied formats.

    Thanks,

    William

  • 0 in reply to William Black
    TI__Guru* 93670 points

    Hi William,

    Thanks for letting me know.

    1). Could you please let me know did you change loop filter using external components or charge pump current registers? 

    2). Also, did you disable Auto Format Detection (AFD) and forced 1080i59.9? 

    Regards,,nasser