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Audio clock generation using FPGA-Attach SER/DES (SDXILIP) RTL IP

prachi panse1
Intellectual 980 points

Hi,

I am using the FPGA-Attach SER/DES (SDXILIP) IP which is available on the Spartan-3A DSP 1800 Development Board. I have a few queries regarding the audio clock scheme.

1. Has the audio interface of the IP been tested in I2S mode?

2. How are the audio bit and word clocks generated as the same is not clear from the logic?

3. We see that the audio phase words are not being extracted from the audio data packets. In that case, how are audio clocks generated? Are audio clocks always generated from video clock assuming it is always synchronous for HD/3G standard?

Also, there is another audio IP SDAUDIOIP available along with the FPGA-Attach SER/DES IP. I have the below queries regarding the same:

1. Is the recovery from 48kHz audio clock from the phase words present in the data packet supported? The logic does not seem to be complete in the RTL.

2. Default value and functionality of the audio_control input register is not mentioned in user guide. Is it possible to share details about the functionality of different bits in the input register?

Please let me know your response on the questions.

Regards,

Prachi

  • 0
    TI__Guru* 93670 points
    Hi Prachi,

    SDAUDIOIP Example code was developed by a 3rd party. This code was not meant to be a complete IP so the user is expected to added additional functionality.

    Could you please let us know about your application and perhaps a block diagram.

    Regards,,nasser