DS90ub940

John

The DS90UB940 does have a built in pattern generator, which is not dependent on the serializer.  For details, please refer to this application note:

http://www.ti.com/lit/an/snla132c/snla132c.pdf

Thank you, that is what I thought, but have another question:
If the CSI output ports are set to replicate, will the result of the pattern generator appear on both CSI0 and CSI1?
The mode is "2 lane FPD-Link III input, 2 MIPI Output (Replicate)". The software development is seeing something different in code in the "MIPI_CSI_PHY_STATE register at iMX6".

This is in addition to my previous post.

Can the DS90UB940 pattern generator run in continuous clock mode with the internal clock reference?

Hi John,

When the 940 is in replicate mode, both ports will output the same content. This also applies to pattern generator mode.

For continuous clock mode, set bit 1 of register 0x6A.

Thanks,
Jason

When the continuous clock mode is enabled, the pattern generator stops working and cannot be re-enabled. Is it possible to run the pattern generator in continuous clock mode and has this been tested by TI? If so, could I get instructions on how to do this. I have been trying multiple configurations and have had no success.
Thanks.

Another question - The EVM guide specifies a DS90Ux940_ENG device.  Is this the same as the DS90Ux940 ?  Just wanted to make sure there was not something else I needed to load as a device.
John

Hi John,

I just tried this in the lab and it does not work. Continuous clock mode only works in non pattern generator mode, when real video is being received. To get this working, do you have a serializer EVM that you could connect to the 940 and configure pattern generator on that device? Then the 940 would be receiving 'real' video.

The ALP profiles for 940 and 940_ENG should be the same except for the register descriptions. The _ENG version has some extra debug registers shown.

Thanks,
Jason

Jason,
I do have a 947 and have tried the serializer pattern generator but wasn't able to verify data makes it through the de-serializer. I see high speed signals on the FDP links but nothing out of the de-serializer. Another problem is that I can't seem to use the same computer using the APF software and view both devices at the same time. Is this normal or am I doing something wrong. Any suggestions on test setup. In addition to the pattern generator, I have a known good LVDS signal driving the video input into the 947 serializer.

Next step is to try the I2c bus for the de-serializer, and ALP software for serializer.

Jason,

I have pictures to attached.  Here is what was performed this morning:  Attached the 947 serializer and ran in both pattern generator (picture 2) and external source mode.  Picture 1 shows the setup with serializer on the left, external source coming in on the yellow, white and black cables.  The blue and white twisted pars are the FPD link 0 and 1 lines.  The deserializer is set for replicate mode, so I am looking at clock on one port and data on another.  (yes, have verified I get the same results on both).  Picture 3 shows the waveform just before I click apply values in picture 4.  When I do that, the signal goes flat line.

Could you please attach a serializer into your setup and see if you can get continuous clock mode working with the serializer pattern generator running.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/TI-SERDES.7z

Hi John,

I don't notice anything unusual about your setup from the pictures. Can you try disabling the CSI-2 output before enabling continuous clock mode then re-enabling?

0x02[6] = 1

0x02[7] = 0

0x6A[1] = 1

0x02[7] = 1

Let me know if that works, and I'll work on getting that setup in our lap to try as well. 

Jason,

That did not seem to make a difference.

A couple of other notes:

1. Could you look at the labeling of J15 and 16 on the Eval board.  Is the silk screen correct?  It shows clock for J16 to be on pin 14 (C1-/CSI1_d0+), when I think it is actually on pin 18.  I have measured both and still do not see the continuous clock.

2. In the TI Analog Launchpad, for register 0x6a, there are 2 locations where bit [6] are defined.  Is this an error and is the one associated with bit [7] incorrect.  When bit [1] is selected, the value changes to 01, where if the register is displayed correctly, it should change by 02.

Are you using the Analog Launchpad to set register values when you do testing?

Jason,

I wanted to post a final finding.  Register 0x6A-csicfg0 in the TI Launchpad V1.54.0010 appears to have an error in the user interface.  To enable continuous clock mode, bit 2 (ULPS) must be selected.  When this is done, the “value” to be written into the register is “02” which is the correct value.  Operation has been verified with the pattern generator running.  Clicking and applying this value can toggle on and off continuous clock mode.

John