• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 32 subscribers
  • Views 744 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN75DP130SS I2C continous reads clarification

hamasaki1818
Intellectual 370 points
Other Parts Discussed in Thread: SN75DP130

We're using SN75DP130SS for a project. Instead of using it in GPIO-driven mode, we are doing some settings on it via I2C. The schematic was previously posted by this account in a separate thread. The hardware has now been tested and works correctly. DP link amplification is confirmed, and the IC is drawing ~130mA in 4 lane HBR mode.

Writes are working correctly (confirmed by using power off and other functions), but reads are strange.

This device doesn't have subaddressing, and datasheet says it will just return all registers from offset zero until host returns NAK. This is all fine and well. So we setup a simple read transaction on the host:

0x59(R) RD RD RD RD ... 39 times STOP.

On first read, we get 0x08, 0x00, 0x14, 0x00, 0x00.... etc

If we then go and read again, we just get 0x00, 0x00, 0x00.... until end of read.

IC is rated at 100kHz I2C and that's what we're using.

Datasheet page 25 "read the SN75 I2C registers" procedure is followed.

How can we get consistent reads out of the device?

  • 0
    TI__Mastermind 23815 points

    Hi Hamasaki,

    Could you please try writing the starting address before reading?

    This is part of the script that I use for reading,


    =====READ first 8 registers
        <i2c_write addr="0x2c" count="1" radix="16">00</i2c_write>
        <i2c_read addr="0x2c" count="8" radix="16"/>

    Please let me know if this solves your problem.

    Regards

  • 0 in reply to Moises Garcia
    Intellectual 370 points

    Err, but that would be against the specification:

    Page 25 of SN75DP130 datasheet:

    The following procedure is followed to read the SN75DP130 I2C registers:

    1. The master initiates a read operation by generating a start condition (S), followed by the SN75DP130 7-bit address and a one-value

    "W/R" bit to indicate a read cycle

    2. The SN75DP130 acknowledges the address cycle

    3. The SN75DP130 transmit the contents of the memory registers MSB-first starting at register 00h.

    4. The SN75DP130 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the

    I2C master acknowledges reception of each data byte transfer

    5. If an ACK is received, the SN75DP130 transmits the next byte of data

    6. The master terminates the read operation by generating a stop condition (P)

     

    No sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the

    registers until the I2C master terminates the read operation.

  • 0 in reply to hamasaki1818
    TI__Mastermind 23815 points
    I know, please try it.
  • 0 in reply to Moises Garcia
    Intellectual 370 points

    Yes, it works, and reads are consistent.



    Why? Does that mean we *can* actually use subaddressing?

  • 0 in reply to hamasaki1818
    TI__Mastermind 23815 points
    Hi Hamasaki,

    It seems you need to use subaddressing because the register address counter is not resetting.
    I have to report this.

    Thanks,
    Regards
  • 0 in reply to Moises Garcia
    Intellectual 370 points

    Well, that makes sense.

    Also looking at the 1st post again, the 1st screenshot reads returned were actually starting from register 0x17 (this is where things were written last, before reads). So it seems subaddressing does exist and/or work, or at least subaddress counter is kept during writes.

    So if possible, can you check into this and get an official confirmation from hardware people that this will work in any revision/datecode of this IC, etc?

    If subaddressing can be used it would actually help a lot because we need to read some DPCD registers and re-reading 40+ registers each time is annoying, but this would need to be always available and not hardware revision dependent.

    EDIT: and if this is official/supported by all hardware revisions, perhaps datasheet needs to be amended?

  • 0 in reply to hamasaki1818
    TI__Mastermind 23815 points
    Hi Hamasaki,

    It seems sub-addressing should be supported in all hardware revisions.
    Datasheet will be amended, there is not an ETA for the change.

    Regards