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TLK10031 10G Ethernet Info

Nicolas V
Prodigy 225 points
Other Parts Discussed in Thread: TLK10031, CDCM7005, TLK10232, CDCM6208, TLK10002

I am designing a 10GbE link between our systems and a PC (equiped with a standard 10GbE NIC) through a TLK10031 connected to a SFP+ optical transceiver (10GBASE-SR) and I want to be sure that this setup is fully compatible with standard 10GbE PCIe NIC commonly used in PC.

The datasheet indicate that the TLK10031 is designed for backplane 10GbE interface (10GBASE-KR). It also indicate that the TLK10031 can be connected to a SFP+ optical transceiver. My question : Is the TLK10031 connected to a SFP+ optical transceiver (10GBASE-SR) fully complies with the 10GBASE-SR standard ?

Thanks.

  • 0
    TI__Mastermind 31600 points
    Nicolas,

    I moved your post to the Consumer & Computing forum so that it gets visibility from the experts for that product.

    Patrick
  • 0
    TI__Genius 16150 points

    Hi Nicolas,

    The TLK10031 is fully compliant with 10GBASE-KR although is able to interface with optical modules (SFP+). So, the electrical interface for an SFP+module supporting, say, 10GBASE-SR would be SFI).

    The datasheet does not mention that is fully compliant with SFP+ (just interfacing with this modules) because the characterization was performed for 10GBASE-KR. Several customers are able to linkup the device (TLK10031/232) with SFP+ modules, so, we know that our device is able to support this protocol.

    Please let me know if you need more information about the procedures to initialize the device in this mode to support 10GBASE-SR.

    Best Regards,

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Prodigy 225 points
    Thank you Luis,

    You say that "several customers are able to linkup the device (TLK10031/232) with SFP+ modules". We are looking for a device that will operate quickly to get a deliverable product as soon as possible. With good high-speed PCB design (good routing pratices and low-noise power supplies), is getting a low-error rate link pretty straightforward or does it require weeks of tweeking ?

    What would be the expected BER with this setup ?

    If you could provide me with the procedures to initialize the device to support 10GBASE-SR, it would be realy appreciated.

    Thank you again.

    Nicolas
  • 0 in reply to Nicolas V
    TI__Genius 16150 points

    Hi Nicolas,

    This device requires an equalization (adjust several parameters) according to the system that is implemented (AC losses, length of traces, among others). Once, the user get the best combination of parameters for the device, the BER is very low, even the GUI has some options to help to get the best combination of values for the equalization.

    For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training.

    To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2.　Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096

    5. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would

    normally be configured through KR training to be configured manually instead.

    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  

    This can be a starting point, but you may need to do some BER testing to optimize the values.

    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3. (At this point the device should be properly configured).

    Best Regards,

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • 0 in reply to Luis Omar Moran
    Prodigy 225 points
    Hi Luis,

    There is another point that I want to dicuss. The datasheet (TLK10031) show an External clock connections circuit (section 10.1.2.2, figure 10-5). What is the objective of using this architecture instead of a simple 156.25MHz low-jitter clock oscillator connected directly to the REFCLK input ?

    Thanks again for your help. It is realy helping.

    Nicolas.
  • 0 in reply to Luis Omar Moran
    Prodigy 225 points
    Hi Luis,

    Could you please give me feedback on my last question ?

    Thank you.

    Nicolas
  • 0 in reply to Nicolas V
    TI__Genius 16150 points

    Hi Nicolas,

    Basically, user can implement a clock jitter cleaner if the application needs a low jitter reference clock. We recommend the CDCM7005 due to this device was implemented in our EVM.


    Best Regards,
    Luis

  • 0 in reply to Luis Omar Moran
    Prodigy 225 points
    Hi Luis,

    I understand your point but my question was more about the possibility of using a local low-jitter clock to drive the TLK10031 REFCLK instead of using the recovered clock from the received data to drive (through a PLL) the the TLK10031 REFCLK.

    In order to clarify the question, could you please answer to following questions:

    1. Is it mandatory to drive the TLK10031 REFCLK with a clock synchronised with the TLK10031 CLKOUT (recovered clock from the received data on the high-speed 10Gb link) ?

    2. What is the system-level benefit of having a REFCLK synchronised with the recovered clock from incoming data on the high-speed link (CLKOUT) ?

    3. We need a reliable design with low BER on the first PCB revision. In this perspective, do you recommand driving the REFCLK with a high quality Crystal Oscillator (Total Stability: +-20ppm; Phase Jitter from 12 kHz to 20 MHz: 0.7ps RMS (max)) through a fanout clock buffer (Additive phase jitter from 12kHz to 20MHz: 95 fs (max)) ?

    4. In the TLK10232 evaluation module, the REFCLK is generated from a simple Clock gererator feed with a Clock Oscillator. Then, I assume that it would be a good practice to drive the REFCLK from a local Crystal oscillator without synching to the recovered clock (CLKOUT) ?

    Thanks you again.

    Nicolas.
  • 0 in reply to Luis Omar Moran
    Prodigy 225 points
    Hi Luis,

    I would appreciate if you could give me feedback on my post of January 14th.

    Thank you again for your help.

    Nicolas
  • 0 in reply to Nicolas V
    TI__Genius 16150 points
    Hi Nicolas,

    Using a local low-jitter clock to drive the TLK10232 REFCLK instead of using the recovered clock from the received data is possible to do for Ethernet applications since CTC(Clock Tolerance Compensation) can be used to compensate for any small differences in frequency between the local and remote reference clock. We recommend using a clock synthesizer IC along with a crystal or crystal oscillator to provide a low-jitter differencial clock signal to the REFCLK inputs. Examples would include CDCM6208 with the TLK10002 or one of the LMK series of devices from SVA.

    In the next link you will find an application note that talks about the combined performance of CDCM6208 with the TLK10002:

    www.ti.com/.../scaa122.pdf.

    Note. The TLK10002 is a pretty similar device than TLK10232, basically is the predecessor.

    Best Regards,
    Luis