DS90LV2422: Deserializer Lock Time

Hi Toshi-san,

I looked back on some of our data when evaluating the part DS92LV2422. In order to bound the deserializer PLL lock time, we would need a non-negligible long test time per part to determine a distribution. Therefore, a typical value was chosen based on the average lock time measured during silicon validation.

We cannot specify a fixed variation in lock time that can normally be guaranteed in the datasheet as a minimum and maximum specification. However, I would expect that it is possible to observe deserializers exhibiting lock times of 10-20 ms in some cases at 75 MHz.

Thanks,

Michael