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C6205 PCI interface read performance across XIO2000A

Andrew Elder
Expert 1680 points
Other Parts Discussed in Thread: XIO2000A, XIO2001

 

We have 2 designs that use a C6205 to perform PCI bus mastering operations. They are as follows

1) PCIe bus <->XIO2000A <-> C6205

2) PCI bus <-> C6205

In both cases the C6205 is clocked at the same rate. With a scope I have measured the read transfer time for 4096 bytes of data. I get

1) 500 usec, with implies a data rate of 8.2 Mbytes/sec

2) 80 usec, with implies a data rate of 51 Mbytes/sec

Why/how does the XIO2000A slow the read performance down so much ? Note that I am running identical code on the C6205 in both tests and

the transfers are to internal C6205 on-chip memory.

 

I did read that the XIO2001 documents that it improves read performance, but I have been unable to locate a description of the XIO2000A read

performance issue that the XIO2001 "fixes".

 

- Andrew

  • 0
    TI__Mastermind 27890 points

    Andrew,

    Due to the nature of bridges, and more specifically PCIe to PCI bridges, there will be a significant performance impact when executing upstream reads. Many factors play into this degradation, including packet size, host chipset latency, upstream bus saturation and others.

     

    The XIO2001 significantly improves upstream memory reads via its speculative read agent function. Please see the following document for more information regarding this funcitonality and other differences between these two parts:

     

    http://www.ti.com/litv/pdf/scpa046