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DP83867IR timing information

Mahendra Patel1
Expert 3560 points
Other Parts Discussed in Thread: DP83867IR

Hello Team,

I have got couple of queries related to DP83867IR,

1)     As per DP83867IR datasheet,

  1. what does the parameterTskewR signify? Does it represent Input side skew inside IC which delays the clock w.r.t. data by min 1ns and max. 2.6ns before latching.
  2. How this parameter affects the setup and hold time requirement at receiver? Pls. provide the formula.

2)      As per RGMIIV2.0_V1.3_timing_appnote.pdf (SNLA243) shows on page 4, Min SR as 0.5ns and MinHr as 0.25ns; however there is no co-relation to setup and hold time as provided by datasheet on page 18. Please clarify.

Regards,

Mahendra Patel

  • 0
    TI__Mastermind 19780 points
    Hi Mahendra,

    Thank you for inquiring about the RGMII timing app note.

    1. The app note used to contain diagrams for RGMII v1.3 and v2.0 standards. A future revision will remove TskewR which is related to RGMII v1.3 and is the amount of delay between CLK and DATA signals introduced by PCB layout.
    2. TskewR can be used in place of TskewT in equations (1) and (3) in the app note.
    3. The datasheet values shall be followed. These values will be updated in the future.

    Best Regards,