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DS90UH926 pixel clock edge select

Gianluca Perrina
Prodigy 110 points

Hi,

I'm changing the value of RRFB bit (addr 0x03 bit 0) pixel clock edge select on DS90UH926 deserializer.

The problem is that datasheet asserts logic 1 as rising edge. Apparently this value is inverted: I mean logic 0 rising edge and logic 1 falling edge.

Is it a known documentation issue?

Thank you and best regards,

Gianluca