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The procedure for linking DS32ELX0421 to DS32ELX0124

tsuyoshi tokumoto
Expert 2630 points
Other Parts Discussed in Thread: DS32ELX0421, DS32ELX0124, TPD1E01B04, DS32EL0421

Dear specialists,

  Please let me ask a question about the correct procedure for linking
  DS32ELX0421 to DS32ELX0124.

  I understand the procedure of linking one DS32ELX0421 to one DS32ELX0124
  by Application Report SNLA109A.
 
  However,my customer is considering connecting one DS32ELX0421 to a number
  of DS32ELX0124 with the DC-balance feature active.
  　  *Cf. attached file FPGA_Link_question.xlsx
  FPGA_Link_question.xlsx


  Could you please tell me how to successfully establish a link under the
  conditions of the above?   
 

Best regards.
Tsuyoshi Tokumoto

  • 0
    TI__Mastermind 29655 points
    Hi Tokumoto-san,

    You should be able to establish link by enabling the DC-balance feature and periodically running SYNC patterns through the cascade to ensure link-up.

    We have historically seen successful applications where one serializer is connected to multiple deserializers by using the retimed output of the DS32ELX0124. The only downside by using this type of setup is that you will not be able to access the back-channel "Remote Sense" feature to ensure constant data alignment and lock. This is because the cascaded deserializers are connected to the retimed output of another deserializer and not a DS32ELX0421 serializer. However, this is not critical, since the DC-balance feature is still useful to ensure data alignment.

    Please refer to the Device Configuration section on p. 15 of the DS32ELX0124 datasheet when Remote Sense is Off and DC Balance is On:

    If DC-Balance is enabled and Remote Sense is disabled (RS# = H and DC_B# = L), an external device should toggle the Data Valid input (TXIN4+/-) to the serializer periodically to ensure constant lock. During this time, the Data Valid input to the serializer must be held high periodically (about once every 500 us) for 110 LVDS clock periods to allow the deserializer to extract the clock and perform lane alignment while skipping the Link Acquisition State. Sending these SYNC signals allwos the receiving system to reacquire lock in case a problem has occurred.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

    Thank you very much for your prompt reply and detailed explanations.
    I described the procedure for linking that I understood from your reply
    in attached file.
    　 *Cf. attached file FPGA_Link.xlsx

    FPGA_Link.xlsx

    Is my understanding correct?

    Please let me ask an additional question.

    Is it necessary to confirm lock signals of deserializers
    in the establishing the link?

    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to tsuyoshi tokumoto
    TI__Mastermind 29655 points
    Hi Tokumoto-san,

    Yes, from your diagram, your proposed link process makes sense to me.

    It would be helpful to confirm that the deserializer is locked by monitoring the LOCK output of the deserializer when establishing link. Usually this is done by the back-channel Remote Sense pin. The link process discussed earlier is under the assumption that you do not have access to the Remote Sense status. Therefore, to assure that the deserializer remains locked (check approximately every 500 us), this link process acts as an alternative method to ensure that the deserializer does not drop out of lock during data transmission. If the link is somehow broken, the training sequence every 500 us will give the deserializer an opportunity to re-lock.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

    　Thank you very much for your prompt reply and the detailed explanations.

    　I understand your reply.

    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

      Please let me ask you three basic questions about
      DS32ELX0421 and DS32ELX0124 when DC-Balance is
      enabled and Remote Sense is disabled.

    Q1) I understand that if the PLL of the serializer has locked
           to the input clock(TxCLKIN),the DS32ELX0421 will enter the
           NORMAL state and the LOCK signal of DS32ELX0421 will go low.
               *There are only 2 states(IDLE and NORMAL).

           Is my understanding correct?


    Q2) I understand that if the CDR of the deserializer has locked
           to the input clock,the DS32ELX0124 will enter the CLOCK ACQUISITION state
           and the LOCK signal of DS32ELX0124 will go low.
                *There are only 3 states(IDLE and CLOCK ACQUISITION and NORMAL).

           Is my understanding correct?


    Q3) I understand that if the TxOUT1(D1) of DS32ELX0124 is used,
            TxOUT0(D0) and TxOUT1(D0) will output same data with same timing.

           Is my understanding correct?


    Thank you very much for your cooperation.


    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to tsuyoshi tokumoto
    TI__Mastermind 29655 points
    Hi Tokumoto-san,

    Thanks for your patience. I have reviewed your questions and have the following responses below:

    1. Since RS# = H, the device will go straight to NORMAL state when lock is achieved with TXCLKIN. Your understanding is correct.

    2. Since RS# = H, the device will go from IDLE to CLOCK ACQUISITION when RxIN is detected and CDR is locked. Your understanding is correct.

    3. I believe you are correct. I checked through the documentation and it appears that as long as TxOUT1_EN is tied high, TxOUT1 will output the same data with the same timing as TxOUT0.

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,


    　　I appreciate your thoughtful reply.


    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

    Please let me ask you two questions.

    My customer is designing a proto type using DS32ELX0421 and DS32ELX0124.

    Q1)He plans to connect one DS32ELX0421 to six DS32ELX0124.
           Is there a limit to the max number of deserializer?

    Q2)The serializer connects with four deserializers establishing a link at first.
           In addition,a link process continues being input every 500us.
              *cf. attached file FPGA_Link.xlsx

    3487.FPGA_Link.xlsx

         After that, if two deserializers are initialized by SMbus,
        will it be possible to add those two deserializers to that connection by connecting cable?
          (hot-swapping)

        Or,is resetting or power off necessary?


    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to tsuyoshi tokumoto
    TI__Mastermind 29655 points
    Hi Tokumoto-san,

    1. There is ultimately going to be a limit the maximum number of deserializers, because there will be jitter peaking from the PLL of each CDR circuit, which will then accumulate in each redundant signal as it passes through more and more DS32ELX0124 deserializers. While this issue may not be enough to cause problems with 6 devices, it may be problematic when you try to daisy-chain a much larger number of DS32ELX0124s. Unfortunately, I do not have any data about the maximum number of deserializers we can support. Nevertheless, I do not anticipate that 6 deserializers should present an issue.

    2. From what I see in the datasheet, a hot swap to add the deserializer in the link should be do-able without resetting or performing a power-off. The deserializer will sit in the IDLE state until RxIN is detected, after which it will go through clock acquisition and normal operation. I believe this behavior will be the same, no matter if the system is powered up and the deserializer is already attached or if the system is powered up and the deserializer is attached later.

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

    Thanks to a lot of your support,my customer
    prototype that the DS32ELX0421 and DS32ELX0124
    are mounted is working correctly.

    However,I would like you to lend me your expertise again.
    Please see the attached file.

    FPGA_Link_question3.xlsx

    My customer would like to use the 20m length cable to
    the Cable1,but when the Cable1 length is 20m,the link is broken.
    (When the Cablel length is 10m,the link is OK)

    The de-emphasis(DS32ELX0421) and equalizer(DS32ELX0124) settings
    that he sets currently are as follows.
    　　１)De-emphasis
    　　　　　de-emphasis：OFF

    　　2)Equalizer
    　　　　　equalizer：Low
    　　　　
    I think the following settings are better than the above settings.
    　　１)De-emphasis
    　　　　　de-emphasis：Mid or High

    　　 2)Equalizer
    　　　　　equalizer：Mid

    Is my understanding correct?
    In addition, could you give me some good advice on this matter?

    Please let me know if there is any necessary information.

    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to tsuyoshi tokumoto
    TI__Mastermind 29655 points

    Hi Tokumoto-san,

    Glad to hear that your customer is making progress in this system design!

    When you extend the link with longer cable, I expect that you will need to have more de-emphasis on the Tx side and more equalization on the Rx side in order to bring the link up.

    In your situation, it looks like you may need medium de-emphasis and mid to high equalization. I agree with the direction you are going with your customer recommendation. Typically in signal conditioning systems, I have observed that it is usually more optimal to use more gain in the Rx EQ instead of more Tx de-emphasis, When using de-emphasis, the low frequencies are attenuated, whereas high frequencies approach unity gain. This is advantageous for overcoming the attenuation effects of long cable on high frequency content, but it also comes at he expense of a lower overall voltage swing at the Rx input. Therefore, when tuning this SerDes pair, I would recommend experimenting with higher EQ settings compared to the Tx settings first. 

    To get a better understanding of the signal quality, it will also be helpful if the customer has some way to determine the signal quality as they change settings. This could be in the form of an eye diagram measured right at the 0421 Rx input, for example.

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Hi Michael-san,

    Thank you for your continued cooperation.

    I understand your recommendation.

    I suggested re-evaluation to my customer with changing the de-emphasis(Mid)
    and the equalization(Mid or High) settings.

    In addition, I will try to suggest measuring the eye diagram to my customer.

    Please let me contact you if I have any questions. 



    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Hi Michael-san,

      Thank you for your continued cooperation.

      The DS32ELX0421 and the DS32ELX0124 are communicated correctly
      through the cable of 20m length.

      The DS32ELX0421/0124 are almost into Dwin.

      My customer is considering improving the ESD susceptibility of the DS32ELX0421/0124(CML I/O)
      currently just in case.

      According to the following post, an ESD diode that has the small loading
      capacitance(approx. 0.2-0.3 pF) was recommended, so I selected a TPD1E01B04.

        e2e.ti.com/.../531654

      However,I have a question.

      According to the datasheet of the DS32ELX0421/0124,though the criteria of IEC61000-4-2
      isn't described,those devices have the HBM ESD susceptibility of above 8kV.

      On the other hand,the TPD1E01B04 has the ESD susceptibility of 15kV(contact) or
      17kV(Air-gap) on the IEC61000-4-2,but the HBM of the TPD1E01B04 is 2.5kV.

      It seems to me that the ESD susceptibility of the TPD1E01B04 is weaker than
      the DS32ELX0421/0124,if I compare the TPD1E01B04 with the DS32ELX0421/0124 by the HBM spec.

      If we add the TPD1E01B04 to the DS32ELX0421/0124,will the ESD susceptibility improve?

      Please lend me your expertise!


    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to tsuyoshi tokumoto
    TI__Mastermind 29655 points
    Hi Tokumoto-san,

    In most customer cases, there should be enough ESD protection from the DS32ELX0421/0124 to protect the SerDes pair, while also ensuring good performance at high-speed.

    With that having been said, if your customer really desires an ESD diode, the TPD1E01B04 seems like a suitable choice. The overall ESD protection should improve, as the the TPD1E01B04 device will help make the high-speed line more robust.

    The difference in Human Body Model (HBM) values you observed (>8 kV for the DS32EL0421/0124 and 2.5 kV for the TPD1E01B04) should not be an issue. The HBM value relates to the ESD susceptibility of strikes directly to the respective IC, as opposed to strikes on the high-speed line (in other words, strikes to the system). The requirement for the JEDEC standard regarding HBM is that the maximum is at least 500-V, which both of our devices easily meet with margin.

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Hi Michael-san,

      Thank you very much for your detailed explanations.

      I am always helped by your thoughtful reply.

      I understand that.

    Best regards.
    Tsuyoshi Tokumoto

  • 0 in reply to Michael Lu (Santa Clara)
    Expert 2630 points

    Dear Michael-san,

      I would like to consult with you about a EMI reduction of communication
      DS32ELX0421 to DS32ELX0124.

      What kind of data do I need to consult with you?

      In addition, if you have any useful material on this issue,
      could you please share it with me?

       ・I have the following materials.
           - The data sheet of DS32ELX0421 and DS32ELX0124.
           - LVDS Owner's Manual.

      I posted the new issue to the past reply, because you
      understand the background well, and the all past issues
      were cleared up by your advice.

      Should I create a new thread?

    Thank you for your continued cooperation.

    Best regards.
    Tsuyoshi Tokumoto