TMDS171 - Power up sequence

Kawai

Guru 19785 points

Other Parts Discussed in Thread: TMDS171

Hello Team,

For the power up sequence of TMDS171, Td1 range is from 0 to 200us. What happens if user has larger delay time to power up Vcc after Vdd ? Do you strictly need to control this power up timing, Td1 range ? Our customer has ms order delay time.

Best Regards,

Kawai

over 9 years ago

0 Kawai over 9 years ago

Guru 19785 points

Another question is that, does VCC and OE must be at 0V before VDD or VCC rise up to the target voltage ?

Best Regards,
Kawai

0 Moises Garcia over 9 years ago in reply to Kawai

TI__Mastermind 23815 points

Hi Kawai-san,

Regarding the power up sequence, you can have any timing between Vcc and Vdd as long as OE is low.

Just wait at least 100us after Vcc and Vdd are stable to assert OE.

Regards

0 Kawai over 9 years ago in reply to Moises Garcia

Guru 19785 points

Hello Moises-san,

Q). Does that mean you could ignore Td1 ? If so, it may be better to remove this requirement. I was thinking that it may be difficult to control VCC and VDD stabled timing relation by 200us.

Q). When using with "Figure 21. External capacitor controlled OE", I believe that the recommended C=0.1uF (in Figure 61) would always meet the Td2 requirement, am I correct ?

Best Regards,
Kawai

0 Moises Garcia over 9 years ago in reply to Kawai

TI__Mastermind 23815 points

Hi Kawai-san,

Yes, you can ignore Td1 as log as OE is low, you just have to meet Td2. We are working to have clearer specifications.

Supposing both Vcc and Vdd are stable at the same time, 100nF should be enough to meet Td2, however i our EVM we use 200nF.

Regards

0 Kawai over 9 years ago in reply to Moises Garcia

Guru 19785 points

Hi Moises-san,

Thank you for the detail information. We would appreciate it if you could have clearer requirements in the next datasheet update.

Best Regards,
Kawai

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TMDS171 - Power up sequence