DS125DF410EVM, 12 GHz Pattern Generator

Hi Bugra,

Information about the DPS-DONGLE-EVM can be found on the SigCon Architect Tools folder page:  

To acquire a DPS-DONGLE-EVM, you will need to submit a request to dps_marketing@list.ti.com, where one of our product marketers will get in touch with you to discuss acquiring this USB-to-SMBus interface device. For more information about the DPS-DONGLE-EVM, you can also reference the DPS-DONGLE-EVM User's Guide, also found on the SigCon Architect Tools folder page.

In the meantime, if you have an I2C master available, you can still communicate with the DS125DF410 on-board by connecting your SDA/SCL/GND pins with the corresponding communication pins on the EVM. From, here, you can read or write registers by address the DS125DF410 in accordance with the address set by the AD[3:0] pins. Note that the description in our documentation assumes that there is an LSB "0" appended to the 7-bit SMBus address. Thus, for example, when AD[3:0] = 0000'b, the SMBus address is 0x18, but we document the SMBus address as 0x30, since an LSB "0" is appended to indicate an SMBus write. Some I2C programs only want the 7-bit address as opposed to the 8-bit address (with the LSB "0" appended), so just a comment.

While you do not need a DPS-DONGLE-EVM to communicate between PC and DS125DF410EVM, they downside is that you will not be able to use SigCon Architect if you do not have the DPS-DONGLE-EVM to control the device.

Thanks,

Michael

Bugra,

Do you have any signal on the input side of the DS125DF410EVM?

Thanks,

Lee

Burga,

You are correct, it is possible to program the DS125DF410 so that a PRBS signal will be output.  This does not require a signal on the input.  Please note that the VCO is "free-running" in this case, the output datarate will wander around to some degree and will not be exactly 12.0 Gbps

Regards,

Lee

Burga,

Here is a sequence which should enable you to get ~ 12 Gbps data out of the DS125DF410

Program 0xFF to select channel

Channel Register          Write Data          Write Mask          Comment  

0x09                                  0x04                    0x04                     Override divider select

0x09                                  0x80                    0x80                     Override VCO cap count

0x08                                  0x06                    0x1F                     Set VCO cap count to 06'h

0x18                                  0x00                    0x70                     Select divider select to 000'b

0x09                                  0x08                    0x06                     Override charge pump power downs

0x1B                                  0x00                    0x03                     Disable both charge pumps

0x09                                  0x40                    0x40                     Override Loop-filter DAC

0x1F                                  0x12                    0x1F                     Set Loop-filter DAC override value

0x1E                                  0x10                    0x10                     Enable PRBS Generator

0x30                                  0x08                    0x0F                      Enable Digital Clock - set pattern to PRBS9

0x09                                  0x20                    0x20                      Override Loopthru Select

0x1E                                  0x80                    0xE0                     Output MUX Select PRBS Generator

0x0D                                  0x20                    0x20                      PRBS Seed Load

To increase the data-rate, decrease  value of Register Data in 0x08 (Step 3).

To decrease the data-rate, increase value of Register Data in 0x08 (Step 3).

Hi Lee,

Please see my detailed I2C traffic while programming DS125DF410EVM based on your instructions. Please comment, (Something We are missing I guess, not working )

I2C WRITE operation 
********************************************************************
0 2761 0:04.299.625 302.500 us 2 B SP 18 Write Transaction FF FF ..

This line Means that I am writing to the device at address of 18 which is DS125DF410EVM
FF means "REGISTER ADDRESS" FF at the device 18 (DS125DF410EVM)
The following FF means "DATA" Which is written to the "REGISTER ADDRESS" given above for the device given above.

************************************************************************


I2C READ operation
*************************************************************************
0 2762 0:04.310.578 608.300 us 1 B S 18 Write Transaction FF .
0 2763 0:04.311.186 215.500 us 1 B SP 18 Read Transaction A5* .

First we set the reference Register Address as FF
Then Read the DATA from this address which is A5
**************************************************************************

Please see the full list of I2C Transaction below to generate 12 GHZ
************************

0 2757 3:27.760.238 Capture stopped [03/03/16 20:14:00] 
0 2758 0:00.000.000 Capture started [03/03/16 20:14:01] 
0 2759 0:04.281.116 577.100 us 1 B S 18 Write Transaction FF .
0 2760 0:04.281.694 215.500 us 1 B SP 18 Read Transaction A5* .
0 2761 0:04.299.625 302.500 us 2 B SP 18 Write Transaction FF FF ..
0 2762 0:04.310.578 608.300 us 1 B S 18 Write Transaction FF .
0 2763 0:04.311.186 215.500 us 1 B SP 18 Read Transaction A5* .
0 2764 0:04.330.372 576.500 us 1 B S 18 Write Transaction 9 .
0 2765 0:04.330.949 215.500 us 1 B SP 18 Read Transaction E8* .
0 2766 0:04.375.451 302.600 us 2 B SP 18 Write Transaction 09 EC ..
0 2767 0:04.385.634 676.500 us 1 B S 18 Write Transaction 9 .
0 2768 0:04.386.311 215.500 us 1 B SP 18 Read Transaction EC* .
0 2769 0:04.418.058 593.700 us 1 B S 18 Write Transaction 9 .
0 2770 0:04.418.651 215.400 us 1 B SP 18 Read Transaction EC* .
0 2771 0:04.464.899 302.500 us 2 B SP 18 Write Transaction 09 EC ..
0 2772 0:04.475.802 678.500 us 1 B S 18 Write Transaction 9 .
0 2773 0:04.476.480 215.500 us 1 B SP 18 Read Transaction EC* .
0 2774 0:04.506.837 561.800 us 1 B S 18 Write Transaction 8 .
0 2775 0:04.507.399 215.500 us 1 B SP 18 Read Transaction 06* .
0 2776 0:04.529.795 302.500 us 2 B SP 18 Write Transaction 08 06 ..
0 2777 0:04.540.918 693.500 us 1 B S 18 Write Transaction 8 .
0 2778 0:04.541.612 215.400 us 1 B SP 18 Read Transaction 06* .
0 2779 0:04.574.659 609.300 us 1 B S 18 Write Transaction 18 .
0 2780 0:04.575.268 215.400 us 1 B SP 18 Read Transaction 00* .
0 2781 0:04.620.385 302.600 us 2 B SP 18 Write Transaction 18 00 ..
0 2782 0:04.630.873 728.400 us 1 B S 18 Write Transaction 18 .
0 2783 0:04.631.602 215.400 us 1 B SP 18 Read Transaction 00* .
0 2784 0:04.661.793 678.300 us 1 B S 18 Write Transaction 9 .
0 2785 0:04.662.472 215.400 us 1 B SP 18 Read Transaction EC* .
0 2786 0:04.707.459 302.700 us 2 B SP 18 Write Transaction 09 E8 ..
0 2787 0:04.717.617 725.600 us 1 B S 18 Write Transaction 9 .
0 2788 0:04.718.343 215.500 us 1 B SP 18 Read Transaction E8* .
0 2789 0:04.750.545 578.800 us 1 B S 18 Write Transaction 1B .
0 2790 0:04.751.124 215.400 us 1 B SP 18 Read Transaction 00* .
0 2791 0:04.796.466 302.500 us 2 B SP 18 Write Transaction 1B 00 ..
0 2792 0:04.806.829 875.200 us 1 B S 18 Write Transaction 1B .
0 2793 0:04.807.704 215.400 us 1 B SP 18 Read Transaction 00* .
0 2794 0:04.835.751 609.500 us 1 B S 18 Write Transaction 9 .
0 2795 0:04.836.360 215.500 us 1 B SP 18 Read Transaction E8* .
0 2796 0:04.882.558 302.600 us 2 B SP 18 Write Transaction 09 E8 ..
0 2797 0:04.892.916 628.300 us 1 B S 18 Write Transaction 9 .
0 2798 0:04.893.544 215.400 us 1 B SP 18 Read Transaction E8* .
0 2799 0:04.924.206 543.800 us 1 B S 18 Write Transaction 1F .
0 2800 0:04.924.749 215.400 us 1 B SP 18 Read Transaction 52* R
0 2801 0:04.970.537 302.700 us 2 B SP 18 Write Transaction 1F 52 .R
0 2802 0:04.980.900 708.800 us 1 B S 18 Write Transaction 1F .
0 2803 0:04.981.609 215.400 us 1 B SP 18 Read Transaction 52* R
0 2804 0:05.012.555 592.700 us 1 B S 18 Write Transaction 1E .
0 2805 0:05.013.148 215.300 us 1 B SP 18 Read Transaction 99* .
0 2806 0:05.059.405 302.500 us 2 B SP 18 Write Transaction 1E 99 ..
0 2807 0:05.069.873 842.600 us 1 B S 18 Write Transaction 1E .
0 2808 0:05.070.716 215.400 us 1 B SP 18 Read Transaction 99* .
0 2809 0:05.101.733 562.900 us 1 B S 18 Write Transaction 30 0
0 2810 0:05.102.296 215.500 us 1 B SP 18 Read Transaction 08* .
0 2811 0:05.148.158 302.500 us 2 B SP 18 Write Transaction 30 08 0
0 2812 0:05.158.841 742.900 us 1 B S 18 Write Transaction 30 0
0 2813 0:05.159.584 215.400 us 1 B SP 18 Read Transaction 08* .
0 2814 0:05.189.451 562.700 us 1 B S 18 Write Transaction 9 .
0 2815 0:05.190.013 215.400 us 1 B SP 18 Read Transaction E8* .
0 2816 0:05.232.476 302.700 us 2 B SP 18 Write Transaction 09 E8 ..
0 2817 0:05.243.179 629.000 us 1 B S 18 Write Transaction 9 .
0 2818 0:05.243.808 215.400 us 1 B SP 18 Read Transaction E8* .
0 2819 0:05.274.095 543.200 us 1 B S 18 Write Transaction 1E .
0 2820 0:05.274.638 215.400 us 1 B SP 18 Read Transaction 99* .
0 2821 0:05.320.785 302.600 us 2 B SP 18 Write Transaction 1E 99 ..
0 2822 0:05.331.883 858.400 us 1 B S 18 Write Transaction 1E .
0 2823 0:05.332.742 215.400 us 1 B SP 18 Read Transaction 99* .
0 2824 0:05.361.748 595.500 us 1 B S 18 Write Transaction 0D .
0 2825 0:05.362.344 215.400 us 1 B SP 18 Read Transaction 20* 
0 2826 0:05.408.541 302.400 us 2 B SP 18 Write Transaction 0D 20 . 
0 2827 0:05.418.859 808.400 us 1 B S 18 Write Transaction 0D .
0 2828 0:05.419.668 215.500 us 1 B SP 18 Read Transaction 20* 
0 2829 0:13.614.648 Capture stopped [03/03/16 20:14:15]

Hi,

There is an issue while writing and reading DS125DF410EVM registers. Not All registers and Not all bits in each register can be written and read. Data sheet is not clear about this. Any suggestions? For example register 0x14 is one of the main register to setup Free VCO PRBS mode and I couldn;t write this register while I can write some of the other registers.

Thanks and best regards,

Hi Bugra,

What are you using to read/write the registers?  Channel register 0x14 is RW for all 8 bits.

Please try to read all the registers and attach them in a text file.

Thanks and Regards,

Lee

Bugra,

The values for FF look incorrect.

When first powered up, reading 0xFF = 00'h

Please read the shared register space 0x00 - 0x07 and 0xFF

Please read the beginning of the channel register space  

Write 0xFF = 05'h

Read 0x00 - 0x0F

Thanks,

Lee

Hi Bugra,

If possible, please consolidate your responses into one post so that it is easier to read. We will do our best to respond to your questions as they come.

1. The "Write Mask" is a mask that we typically use to describe the bits that are changed in the register write process. You can think of this as performing an "AND" logical operation with the Write Data and the performing an "OR" with the existing contents of the register. So, as an example, if the Write Data is 0x04, the Write Mask is 0x0F, and the existing contents of the register is 0xA2, then only the 4 LSBs are set, since the write mask has all 1's for the 4 lower bits. All bits that are listed as 0 in the Write Mask are not changed. So, in this example, the resulting register value will become 0xA4. This is what we mean by Write Mask.

2. Yes, if you write 0x0F to Reg 0xFF, you will be able to broadcast a write to all channels. When you read back, you will only read the contents of Channel 3.

3.The contents of Reg 0xFF cannot be read back in SMBus. A read operation will yield an invalid result. Therefore, even though you read 0xA5 back, the DS125DF410 should have accepted the value you last programmed into Reg 0xFF according to Table 15 in the datasheet. This behavior is documented in Section 7.6.4 of the DS125DF410 datasheet. There should not be a need to perform any kind of update before writing to Reg 0xFF.

4. I believe Lee has helped to address you question about the register dump by suggesting that there is an issue with Reg 0xFF. Bits 7:4 are reserved, so please ensure that you do not write 1111'b to these bits. Please let us know if this solves the issue.

5. The external clock is not mandatory. The external clock serves as a VCO calibration reference only (see Section 7.5.21), and it is used as a calibration tool for the internal VCO to improve lock time. Since you are planning to use this device in free-run mode, there is theoretically no input signal to lock to.

6. I am not sure how you are calculating Reg 0x1E = 0xA0. You must first write Reg 0x1E[4] = 1 to enable the PRBS generator. Then, you must set Reg 0x1E[7:5] = 100'b to change the output mux to be the PRBS output, which we do later in the sequence. I believe this second part is the one you are asking about. This will ultimately give you a result of Reg 0x1E = 0x90 (not 0xA0), and you must write the registers in the order Lee showed above. I think your "Solution 1" is partially correct, but you must then set the appropriate output mux select after enabling the digital clock and overriding the output mux selection (labeled in Lee's step as "Loopthru Select").

Thanks,

Michael

Hi Michael and Lee,

After I power up, I read the registers from 0 to 7 and register FF. Please see below:

DS125DF410 Registers
Address:0x0 Data :0x0
Address:0x1 Data :0xd1
Address:0x2 Data :0x0
Address:0x3 Data :0x0
Address:0x4 Data :0x1
Address:0x5 Data :0x0
Address:0x6 Data :0x0
Address:0x7 Data :0x4
Address:0xff Data :0x0

Then I updated the registers as follow:

DS125DF410 Debugging
********************************************************
Register Count = 1
C1-Address I am going to modify : 0xff
C2-Original data at this address: 0x0
C3-The mask I am using: 0xff
C4-First AND operation the mask and the data: 0xf
C5-Second OR operation with the original content 0xf
C5-Writing through I2C -> ADDRESS = 0xff DATA = 0xf
********************************************************
READ BACK TO VERIFY
ADDRESS = 0xff DATA = 0xa5
FAIL    ( Note *** This is expected because of register 0xFF)
********************************************************
********************************************************
Register Count = 2
C1-Address I am going to modify : 0xff
C2-Original data at this address: 0xa5
C3-The mask I am using: 0xff
C4-First AND operation the mask and the data: 0xf
C5-Second OR operation with the original content 0xf
C5-Writing through I2C -> ADDRESS = 0xff DATA = 0xf
********************************************************
READ BACK TO VERIFY
ADDRESS = 0xff DATA = 0xa5
FAIL     ( Note *** This is expected because of register 0xFF)
********************************************************
********************************************************
Register Count = 3
C1-Address I am going to modify : 0x9
C2-Original data at this address: 0x0
C3-The mask I am using: 0x4
C4-First AND operation the mask and the data: 0x4
C5-Second OR operation with the original content 0x4
C5-Writing through I2C -> ADDRESS = 0x9 DATA = 0x4
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x9 DATA = 0x4
PASS
********************************************************
********************************************************
Register Count = 4
C1-Address I am going to modify : 0x9
C2-Original data at this address: 0x4
C3-The mask I am using: 0x80
C4-First AND operation the mask and the data: 0x80
C5-Second OR operation with the original content 0x84
C5-Writing through I2C -> ADDRESS = 0x9 DATA = 0x84
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x9 DATA = 0x84
PASS
********************************************************
********************************************************
Register Count = 5
C1-Address I am going to modify : 0x8
C2-Original data at this address: 0x0
C3-The mask I am using: 0x1f
C4-First AND operation the mask and the data: 0x6
C5-Second OR operation with the original content 0x6
C5-Writing through I2C -> ADDRESS = 0x8 DATA = 0x6
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x8 DATA = 0x6
PASS
********************************************************
********************************************************
Register Count = 6
C1-Address I am going to modify : 0x18
C2-Original data at this address: 0x40
C3-The mask I am using: 0x70
C4-First AND operation the mask and the data: 0x0
C5-Second OR operation with the original content 0x0
C5-Writing through I2C -> ADDRESS = 0x18 DATA = 0x0
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x18 DATA = 0x0
PASS
********************************************************
********************************************************
Register Count = 7
C1-Address I am going to modify : 0x9
C2-Original data at this address: 0x84
C3-The mask I am using: 0x6
C4-First AND operation the mask and the data: 0x0
C5-Second OR operation with the original content 0x80
C5-Writing through I2C -> ADDRESS = 0x9 DATA = 0x80
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x9 DATA = 0x80
PASS
********************************************************
********************************************************
Register Count = 8
C1-Address I am going to modify : 0x1b
C2-Original data at this address: 0x3
C3-The mask I am using: 0x3
C4-First AND operation the mask and the data: 0x0
C5-Second OR operation with the original content 0x0
C5-Writing through I2C -> ADDRESS = 0x1b DATA = 0x0
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x1b DATA = 0x0
PASS
********************************************************
********************************************************
Register Count = 9
C1-Address I am going to modify : 0x9
C2-Original data at this address: 0x80
C3-The mask I am using: 0x40
C4-First AND operation the mask and the data: 0x40
C5-Second OR operation with the original content 0xc0
C5-Writing through I2C -> ADDRESS = 0x9 DATA = 0xc0
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x9 DATA = 0xc0
PASS
********************************************************
********************************************************
Register Count = 10
C1-Address I am going to modify : 0x1f
C2-Original data at this address: 0x55
C3-The mask I am using: 0x1f
C4-First AND operation the mask and the data: 0x12
C5-Second OR operation with the original content 0x52
C5-Writing through I2C -> ADDRESS = 0x1f DATA = 0x52
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x1f DATA = 0x52
PASS
********************************************************
********************************************************
Register Count = 11
C1-Address I am going to modify : 0x1e
C2-Original data at this address: 0xe9
C3-The mask I am using: 0x80
C4-First AND operation the mask and the data: 0x80
C5-Second OR operation with the original content 0xe9
C5-Writing through I2C -> ADDRESS = 0x1e DATA = 0xe9
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x1e DATA = 0xe9
PASS
********************************************************
********************************************************
Register Count = 12
C1-Address I am going to modify : 0x30
C2-Original data at this address: 0x0
C3-The mask I am using: 0xf
C4-First AND operation the mask and the data: 0x8
C5-Second OR operation with the original content 0x8
C5-Writing through I2C -> ADDRESS = 0x30 DATA = 0x8
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x30 DATA = 0x8
PASS
********************************************************
********************************************************
Register Count = 13
C1-Address I am going to modify : 0x9
C2-Original data at this address: 0xc0
C3-The mask I am using: 0x20
C4-First AND operation the mask and the data: 0x20
C5-Second OR operation with the original content 0xe0
C5-Writing through I2C -> ADDRESS = 0x9 DATA = 0xe0
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x9 DATA = 0xe0
PASS
********************************************************
********************************************************
Register Count = 14
C1-Address I am going to modify : 0x1e
C2-Original data at this address: 0xe9
C3-The mask I am using: 0xe0
C4-First AND operation the mask and the data: 0x80
C5-Second OR operation with the original content 0x89
C5-Writing through I2C -> ADDRESS = 0x1e DATA = 0x89
********************************************************
READ BACK TO VERIFY
ADDRESS = 0x1e DATA = 0x89
PASS
********************************************************
********************************************************
Register Count = 15
C1-Address I am going to modify : 0xd
C2-Original data at this address: 0x0
C3-The mask I am using: 0x20
C4-First AND operation the mask and the data: 0x20
C5-Second OR operation with the original content 0x20
C5-Writing through I2C -> ADDRESS = 0xd DATA = 0x20
********************************************************
READ BACK TO VERIFY
ADDRESS = 0xd DATA = 0x20
PASS
********************************************************

Hi Michael and Lee,

After the steps I followed in my previous message, I don;t see 12GHZ signal at the output of the board. Please comment.

Hi Michael and Lee, 

Is there any suggestions? 

Thanks and best regards,

Hi Lee, 

Found a potential bug in your register, value, mask pair. Please see below:

Instruction:

Register Address            Value                  Mask

0x09                                  0x08                    0x06                     Override charge pump power downs

This Mask and Value don't match each other. What should I use?

Thanks and best regards,

Hi Burga,

I'm the DPS Applications Engineer supporting the retimer product line. I will take the action to verify in the lab that the routine below translates to PRBS pattern being output by the retimer with a data rate of 12 Gbps in VCO free run mode. Once I confirm that the script works, then I will need to understand more about your setup to troubleshoot why you are not seeing the desired result.

                                       Channel Register          Write Data          Write Mask          Comment  

STEP 5 :                              0x09                                  0x08                    0x06                     Override charge pump power downs

Please see the full instruction below to generate 12 GHZ.

Program 0xFF to select channel

Channel Register          Write Data          Write Mask          Comment  

0x09                                  0x04                    0x04                     Override divider select

0x09                                  0x80                    0x80                     Override VCO cap count

0x08                                  0x06                    0x1F                     Set VCO cap count to 06'h

0x18                                  0x00                    0x70                     Select divider select to 000'b

0x09                                  0x08                    0x06                     Override charge pump power downs

0x1B                                  0x00                    0x03                     Disable both charge pumps

0x09                                  0x40                    0x40                     Override Loop-filter DAC

0x1F                                  0x12                    0x1F                     Set Loop-filter DAC override value

0x1E                                  0x10                    0x10                     Enable PRBS Generator

0x30                                  0x08                    0x0F                      Enable Digital Clock - set pattern to PRBS9

0x09                                  0x20                    0x20                      Override Loopthru Select

0x1E                                  0x80                    0xE0                     Output MUX Select PRBS Generator

0x0D                                  0x20                    0x20                      PRBS Seed Load

To increase the data-rate, decrease  value of Register Data in 0x08 (Step 3).

To decrease the data-rate, increase value of Register Data in 0x08 (Step 3).

Expect a response sometime tomorrow (Wednesday Pacific Time.)

Cordially,

Rodrigo Natal

Hi Bugra. There were indeed quite a few issues with the original script that you received, which would prevent a proper TX output. My apologies for that. Below is a corrected script which I confirmed in the lab to set the retimer Tx output on channel 0 to generate PRBS31 pattern of 12Gbps data rate while operating in VCO free run mode.

As a sanity check, after running the script above I connected the channel 0 Tx outputs to the channel 1 Rx inputs, and then configured channel 1 to ref_mode=0 by setting channel register 0x36[5:4] = 00. Channel 1 was able to lock to the channel 0 VCO free run PRBS outtput and the observed eye opening at channel 1 Rx was quite good. See below.

Hi Rodrigo, 

Great! Thank you! I got the signal. 

One more thing on this case:

What about using external reference clock, My error detection equipment(BERT) and pattern generator(TI DS125SF410EVM) needs to be synchronized through reference clock. How can I program this?

This chip has also eye monitoring feature. I wonder is there any way to derive Bit Error Rate or approximate through eye monitoring feature of this chip?

Thanks and best regards,

Hi Bugra,

The DS125DF410 implements a referenceless CDR architecture. The ref_clk that is provided to our device does not actually clock the high-speed data path. The ref_clk  mainly serves as a counter for the the digital circuitry. For your ease of reference I've included a pic below for a BERTScope BERT instrument. This instrument requires a "clock input" signal to synchronize the "error detector". As the DS125DF410 does not have a high-speed clock output, your alternative would be to drive the error detector single-ended with the DS125DF1410, and use the other signal from the DS125DF410 DUT channel pair to drive the clock input. You may terminate the unused signal input on the error detector to 50 ohm.

The horizontal eye opening (HEO) and vertical eye opening (VEO) readings from the DS125DF410 by default correspond to a probability level in the order of 1E-6. Channel register 0x2A (EOM timer threshold) allows the user to control the amount of time the eye monitor samples each point in the eye for. If you maximize the value, the probability level is reduced to a value in the range of 1E-9.

Regards,

Rodrigo Natal

Each retimer channel is independent. What you may be able to do is configure a channel, say channel 0,  to free run PRBS generator mode. You can then use its p output signal to driver retimer channel 1 single ended and its n signal for BERT clock input. Channel 1 Tx can then drive the channel under test differentially and the signal after the channel can be fed to the Rx inputs of channel 2. In this configuration, you would need to set both retimer channel 1 and channel 2 to ref_mode 0 by setting channel register 0x36[5:4)='00', so that they can lock to the ~12Gbps data rate signal generated in free run by channel 0.

Cordially,

Rodrigo Natal

Hi Rodrigo,

I need your guidance about how to make changes in the following script in order to use two channel: One is for the generation of PRBS as we discussed earlier, Second one as retimer:

I am confused about the integration of

" setting both retimer channel 1 and channel 2 to ref_mode 0 by setting channel register 0x36[5:4)='00', so that they can lock to the ~12Gbps data rate signal generated in free run by channel 0."

into the following working script

Register Data Mask Description
FF 4 FF Sel Channel 0
14 80 FF SD Preset Enable
9 EC FF Override charge pump power down, divider select, VCO cap count, LPF DAC, loopthru mux select
1b 0 FF Disable both charge pumps
8 3 FF Set VCO cap count to 03
18 0 FF Set divider to 1
1f 52 FF Set LPF DAC to 12
1e 91 FF Output Mux Select PRBS, enable PRBS Generator
d 20 FF Enable PRBS Clock
30 0 FF Reset PRBS CLK
30 A FF Powerup PRBS Clk, select PRBS31

Hi Bugra. The retimer supports a broadcast mode where channel register write operations are applied to all channels. To enable broadcast mode, set shared register 0xFF[3:2] = '11'.  

Regards,

Rodrigo Natal

Hi Rodrigo, 

Can we use broadcast mode?  Because two channels are different than each other.

Channel 0 and Channel 1 will be different:

Channel 0 will be configured as Free Run PRBS mode.

Channel 1 will be in re-timer mode.

Configuration register contents will be different. 

Channel 0 output will drive the input of Channel 1. Channel 0 input will be ignored but Channel 1 will use Channel 0 as input (single ended)

If I set register FF into broadcast mode, how can we differentiate two channels?

Thanks  and best regards,

Bugra