ds90cf384a & wvga support

Hi Pierre,

Thanks for providing more detailed information in a separate message:

=======================

I work on Android build project with a WVGA screen NHD-5.0-800480TF-ATXL#-CTP.

I use DS90CF384A to translate LVDS to RGB. It seems to work but image is dirty quality. I took a photo of the screen. It displays jpg image on the left, and unvarying colors on the right. You could see on the left, blue and red pixels lines. I also see some blinking pixels.



Here is my display conf in Android :

lvds-channel@0 {
                reg = <0>;
                fsl,data-mapping = "spwg";
                fsl,data-width = <24>;
                crtc = "ipu1-di0";
                primary;
                status = "okay";

/* Capacitive Display */
/*Configuration Newhaven 5.0 */
        display-timings{
                        native-mode = <&timing0c>;
                        timing0c: newhaven5 {
                                clock-frequency = <27600000>; //Also tried 36MHz with same result
                                hactive = <800>;
                                vactive = <480>;
                                hback-porch = <87>;
                                hfront-porch = <41>;
                                vback-porch = <29>;
                                vfront-porch = <16>;
                                hsync-len = <2>;
                                vsync-len = <3>;
                                hsync-active = <0>;
                                vsync-active = <0>;
                                de-active = <1>;
                                pixelclk-active = <1>;
                        };
                };


Do I have bad synchronization between RGB lines ? How your experience could explain this behaviour ?

=======================

It may be possible that you are not quite using the right clock for the display requirements. The 27.6 MHz value we provided is an estimate of the type of pixel clock we anticipate if a 20% blanking period is assumed. From the datasheet, it looks like the pixel clock frequency (DCLK frequency) is around 30-50 MHz. Can you try with 30 MHz as well as match your programmed porch and pulse width values with what is the New Haven Display specs? It looks like your values are a little different:

Thanks,

Michael

Hello Michael,

Thanks for your support with Jamille. Before writing on TI forum, I tried 30 MHz to 45 MHz Dclk conf with same result as 27,6 MHz. If I use typical spec values, the active area is partially out of display screen.

Here is my last try conf. I set hsync-len=48 (typical value) and adjust hback-porch=41 & hfront-porch=87 to center active area. I also set 31 MHz DCLK to reach 60fps (30 MHz = 58 fps).

clock-frequency = <31000000>;
                                hactive = <800>;
                                vactive = <480>;
                                hback-porch = <41>;
                                hfront-porch = <87>;
                                vback-porch = <29>;
                                vfront-porch = <16>;
                                hsync-len = <48>;
                                vsync-len = <3>;
                                hsync-active = <0>;
                                vsync-active = <0>;
                                de-active = <1>;
                                pixelclk-active = <1>;

I took a photo of the screen. It displays jpg image on the left, and unvarying colors on the right. You could see on the left, blue and red pixels lines. I also see some blinking pixels.

I will welcome any investigation ideas.

Best regards, Pierre

Hi Pierre,

I wonder if there may be any corruption on the LVDS lines. If the input signal quality to the DS90CF384A is out of spec from what the DS90CF384A LVDS inputs can tolerate, then we may have an issue with the image at the output. Is it possible to get a scope shot of both the clock and one of the input data channels in the same screen, with both measurements taken differentially across the 100-ohm resistorat the DS90CF384A input?

Also, if you could share a schematic and/or board layout file, that would be helpful as a sanity check.

Regards,

Michael

Hello Michael,

I solved the problem by hard changing PCLK polarity on display ! Image is good quality now. I was sure to software invert PCLK but it wasn't...

Thanks for your support, Pierre

Hi Pierre,

Interesting! Glad to hear that the problem is resolved. It seems that the PCLK polarity on the display was causing some kind of strange sampling timing. Best wishes as you continue with your design, and thanks for providing closure on this.

Michael