DS90CF383B spce of PWRDWN pin

Hi g.f.,

I searched in our archives to determine whether we have information regarding the transition time, and I was not able to find supporting documentation for this part aside from the datasheet. It looks like we can only go by what is in the datasheet.

A1. Yes, since the datasheet states that the PWRDWN pin and the TxIN have the same transition time range, the transition time of 1.5-6 ns applies to the PWRDWN pin.

A2. From my understanding of other FPD-LINK parts, it appears that this requirement is more critical for the TxIN data pins, as the minimum pulse transition time helps to define the minimum transition edge to ensure the ESD structure will not activate, whereas the maximum transition time will help ensure that the ideal setup-and-hold times for data sampling on each falling clock edge is maintained, especially at the highest operating frequency. Note that it is similar to the TxCLK IN max transition time.

A3. If absolutely necessary, the DS90CF383B should be able to function properly if the PWRDWN pin transition time is increased beyond 6 ns. In other FPD-LINK SerDes chipsets, it is common to apply a low-pass RC filter (for example, 10k series and 22uF to GND) on the PWRDWN pin to ensure that the PWRDWN edge does not trigger the internal ESD structure due to voltage overshoot. However, since it is hard for me to say for sure the exact reason for including the PWRDWN pin in the 1.5-6 ns transition time specification of this datasheet, I would try to observe the 1.5-6 ns requirement if you are able to.

Thanks,

Michael