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TLK2701 data reception latency

Holger Arthaber
Prodigy 20 points


The TLK2701's datasheets specifies RX latency to be in the range 76...107 bits and to be constant as the link is established.

Does this mean

a) after a loss of sync or a power-cylcle, the new latency is different. In a design where the RX data bus is connected to an FPGA I would have to readjust the input delays after each power-cycle or loss of sync.

or

b) the latency for a certain silicon is always the same (as long as temperature and voltage is constant). In a design where the RX data bus is connected to an FPGA I could adjust the input delays once (factory calibration). Of course I still would have to expect some small latency variation over temp/voltage in the same order like the TX latency.

Best regards,
Holger

  • 0
    TI__Genius 16150 points

    Hi Holger,

    After of a loss of sync or a power-cycle, the new latency could be different, not necessary a constant value. Basically, our design ensures that the range of RX latency will be 76-107 bit times, hence, the latency will be determined by the silicon process variations and implementation, also, for variations in supply voltaje and temperature.

    Best Regards,

    Luis Omar Morán Serna

    High Speed Inertace

    SWAT Team