Hello,
I am using the DS90UB925/926. When there is a momentary loss of pixel clock, I lose LOCK and my GPIO[0:3] fall low regardless of the previous GPIO state. Is it possible to to have these registers hold their value while the link is periodically down? I haven't been able to probe them (SW isn't ready), but will the GPOs also clear?
Can this be prevented by having the 926 use its internal clock when the pixel clock is lost?