Hi,Team!
The DP159 is used as DisplayPort Retimer in our DisplayPort application.The device is configured and managed by Xilinx FPGA. The Schematic is as same as Example Implementation of SLLA358. Local IIC slave address is 0x5E. My configuration of DP159 is referring to document "Xilinx DisplayPort v6.1 LogicCORE IP Product Guide, PG064 September 30, 2015". But link training is failed with DP source.
From the print information ，I find that the device is trying to link DP source at different data rates.
Could you give us some helpful suggestions to make the device work properly. Thank you very much!
Additional，Could you support the document “DP159 X-Mode Registers (SLLA359)”. I don't find it in TI website.
The configuration is below:
the default value of bandwidth and lane_counter are 0x14 and 0x04.
#include "typedef.h"
#include "xil_types.h"
#include "delay.h"
#include "debug.h"
#include "dp_sink.h"
#include "ps7_init_linkwind.h"
#include "zynq_sdk.h"
#include "ddp.h"
#include "global_timer.h"
#include "ps7_gpio.h"
USHORT ucTickCount=0;
extern unsigned short ucTickCount;
typedef int XStatus;
////////////////////////////////////////////////////////
// InitMessage()
//
// init Urt control and print current Version string
//
//
////////////////////////////////////////////////////////
void InitMessage()
{
// init_printf();
printf("\n");
}
//#define HBR2 //5.4Gbps
//#define HBR //2.7Gbps
//#define RBR //1.62Gbps
void DP159_IIC_Write(u32 reg_addr, u32 data)
{
PSIIC0_Write(DP159_SLV_ADDR, reg_addr, 0x1, data);
}
BYTE DP159_IIC_Read(u32 reg_addr)
{
BYTE rd_data;
rd_data = PSIIC0_Read(DP159_SLV_ADDR, reg_addr, 0x01);
return (BYTE) rd_data;
}
void InitIt_Dp159()
{
//print("Start to Initialize DP159.\r\r\r\n");
//DP159_IIC_Write(0x09, 0x82) ;//swap enable
//Page 0
u32 uc;
DP159_IIC_Write(0xFF, 0x00) ;//Select Page 0
DP159_IIC_Write(0x09, 0x36) ;//Enable X-Mode
DP159_IIC_Write(0x0A, 0x7B) ;//Disable HPD_SNK pass thru to HPD_SRC.
DP159_IIC_Write(0x0D, 0x80) ;//Enable clock on AUX. Select 1/20 mode.
DP159_IIC_Write(0x0C, 0x6D) ;//Set TX Swing to Max
DP159_IIC_Write(0x10, 0x00) ;//Turn off pattern verifier
DP159_IIC_Write(0x10, 0x11) ;//Len = PRBS23, Sel = PRBS mode to turn off char-alignment
DP159_IIC_Write(0x16, 0xF1) ;//Disable char-alignment on all lanes.
DP159_IIC_Write(0xFF, 0x01) ;// Select Page 1
//CONFIGURE PLL BLOCK
DP159_IIC_Write(0x00, 0x02) ; //Enable Bandgap.
DP159_IIC_Write(0x04, 0x80) ; //PLL_FBDIV[7:0]
DP159_IIC_Write(0x05, 0x00) ; //PLL_FBDIV[10:8]
DP159_IIC_Write(0x08, 0x00) ;
DP159_IIC_Write(0x0D, 0x02) ; //Select LN0 for clock.
DP159_IIC_Write(0x0E, 0x03) ; //CDR_CONFIG[4:0]. FIXED, LN0.
DP159_IIC_Write(0x01, 0x01) ; //CP_EN is PLL mode
DP159_IIC_Write(0x02, 0x3F) ; //CP_CURRENT is high.
DP159_IIC_Write(0x0B, 0x33) ; //Loop Filter to 8K.
DP159_IIC_Write(0xA1, 0x02) ; //Allows for Override of PLL settings.
DP159_IIC_Write(0xA4, 0x02) ; //Allows for Override of PLL settings.
//CONFIGURE TX BLOCK
DP159_IIC_Write(0x10, 0xF0) ; //ENTX for all four lanes (disable)
DP159_IIC_Write(0x11, 0x30) ; //TX_RATE is Full Rate, TX_TERM = 75 to 150 , TX_INVPAIR = None
DP159_IIC_Write(0x14, 0x00) ; //HDMI_TWPST1 is 0dB pre-emphasis
DP159_IIC_Write(0x12, 0x03) ; //SLEW_CTRL is Normal, SWING is 600mV.
DP159_IIC_Write(0x13, 0xFF) ; //FIR_UPD. Load TX settings
DP159_IIC_Write(0x13, 0x00) ;
//CONFIGURE RX BLOCK
DP159_IIC_Write(0x30, 0xE0) ; //Disable Receivers except lane 0
DP159_IIC_Write(0x32, 0x00) ; //PD_RXINT
DP159_IIC_Write(0x31, 0x00) ; //RX_RATE is Full
DP159_IIC_Write(0x4D, 0x08) ; //EQFTC = 0 and EQLEV = 8
DP159_IIC_Write(0x4C, 0x01) ; //Enable Fixed EQ
DP159_IIC_Write(0x34, 0x01) ; //Enable Offset correction
DP159_IIC_Write(0x32, 0xF0) ; //Load RX settings.
DP159_IIC_Write(0x32, 0x00) ;
DP159_IIC_Write(0x33, 0xF0) ; //Load EQ settings.
DP159_IIC_Write(0xFF, 0x00) ; //Select Page 0
DP159_IIC_Write(0x0A, 0x3B) ; //Enable HPD_SNK pass thru to HPD_SRC. Retimer
DP159_IIC_Write(0xFF, 0x01) ; //Select Page 1
printf("DP159 Initialization has finished\r\r\r\n");
}
void Tp1_Intr_Handler(u32 link_bw, u32 lane_count)//TP1 Interrupt Handler
{
//HBR2--5.4Gbps,HBR--2.7Gbps,RBR--1.62Gbps
DP159_IIC_Write(0x00, 0x02);//Enable Bandgap, DISABLE PLL, clear A_LOCK_OVR
DP159_IIC_Write(0x01, 0x01);//CP_EN = PLL (reference) mode
DP159_IIC_Write(0x0B, 0x33);//Set PLL control
DP159_IIC_Write(0x02, 0x3F);//Set CP_CURRENT
switch(lane_count&0x0f)
{
case 0x04:
{
DP159_IIC_Write(0x30, 0x0F);//Set RX Lane count ,0xE1--Lane count 1,0xC3--Lane count2,0x0F--Lanecount4
break;
}
case 0x02:
{
DP159_IIC_Write(0x30, 0xC3);
break;
}
case 0x01:
{
DP159_IIC_Write(0x30, 0xE1);
break;
}
default:
{
DP159_IIC_Write(0x30, 0xE1);
break;
}
}
DP159_IIC_Write(0x00, 0x03);//Enable Bandgap, DISABLE PLL, clear A_LOCK_OVR
DP159_IIC_Write(0x4C, 0x01);//Enable fixed EQ
switch(link_bw&0xff)
{
case 0x06:
{
DP159_IIC_Write(0x4D, 0x28);//Set EQFTC and EQLEV (fixed EQ),0x08--HBR2,0x18--HBR,0x28--RBR
break;
}
case 0x0a:
{
DP159_IIC_Write(0x4D, 0x18);
break;
}
case 0x14:
{
DP159_IIC_Write(0x4D, 0x08);
break;
}
default:
{
DP159_IIC_Write(0x4D, 0x08);
break;
}
}
//Determine the PLL lock. If achieved, change PLL mode based on the lane rate. Continue programming,
//after the DP159 PLL lock.
switch(lane_count&0x0f)
{
case 0x04:
{
DP159_IIC_Write(0x10, 0x0F);//Enable TX lanes,0xE1--Lane count 1,0xC3--Lane count2,0x0F--Lanecount4
break;
}
case 0x02:
{
DP159_IIC_Write(0x10, 0xC3);
break;
}
case 0x01:
{
DP159_IIC_Write(0x10, 0xE1);
break;
}
default:
{
DP159_IIC_Write(0x10, 0xE1);
break;
}
}
DP159_IIC_Write(0x00, 0x23);//Enable Bandgap and PLL, set A_LOCK_OVR
switch(link_bw&0xff)
{
case 0x06:
{
DP159_IIC_Write(0x02, 0x1F);
break;
}
case 0x0a:
{
DP159_IIC_Write(0x02, 0x27);
break;
}
case 0x14:
{
DP159_IIC_Write(0x02, 0x5F);//Set CP_CURRENT ,0x5F--HBR2,0x27--HBR,0x1F--RBR
break;
}
default:
{
DP159_IIC_Write(0x02, 0x1F);
break;
}
}
DP159_IIC_Write(0x0B, 0x30);//PLL loop filter 1K
DP159_IIC_Write(0x01, 0x02);//CP_EN is PD mode
DP159_IIC_Write(0xFF, 0x00);//Select Page0
switch(lane_count&0x0f)
{
case 0x04:
{
DP159_IIC_Write(0x16, 0xF1);//Set DP_TST_EN per #lanes, latch FIFO errors,0x11--Lane Count1,0x31--Lane count 2,
//0xF1--Lane count4,0xF1--Set DP_TST_EN on all lanes to disable char-alignment
break;
}
case 0x02:
{
DP159_IIC_Write(0x16, 0x31);
break;
}
case 0x01:
{
DP159_IIC_Write(0x16, 0x11);
break;
}
default:
{
DP159_IIC_Write(0x16, 0x11);
break;
}
}
DP159_IIC_Write(0x10, 0x00);//Disable PV
DP159_IIC_Write(0xFF, 0x01);//Select Page1
printf("TP1 Interrupt Handler has been finished\r\r\r\n");
}
void Tp23_Intr_Handler()//TP23 Interrupt Handler
{
u8 uc;
u8 ud;
DP159_IIC_Write(0x4C, 0x03);//Enable Adaptive Equalization
DP159_IIC_Write(0xFF, 0x00);//Select Page0
DP159_IIC_Write(0x15, 0x18);//Clear BERT counters and TST_INTQ latches
uc=DP159_IIC_Read(0x18);//;Read BERT counters [7:0] read and error counters increment
ud=DP159_IIC_Read(0x19); //Read BERT counters[11:8] read and error counters increment
DP159_IIC_Write(0xFF, 0x01);//Select Page1
if((uc != 0x00)||(ud != 0x00))
{
printf("parallel bit error occurs \r\r\r\n");
}
else {
printf("parallel bit error rate tester Operates normally \r\r\r\n");
}
}
void ReInitIt_Dp159()
{
u32 uc;
DP159_IIC_Write(0x00, 0x02), //Disable PLL and clear A_LOCK_OVR
DP159_IIC_Write(0x34, 0x01), //Enable Offset Correction
DP159_IIC_Write(0x02, 0x3F), //CP_Current is High BW.
DP159_IIC_Write(0x01, 0x01), //CP_EN is PLL mode
DP159_IIC_Write(0x0B, 0x33), //PLL Loop filter 8K
DP159_IIC_Write(0x4D, 0x08), //EQFTC = 0 and EQLEV = 8
DP159_IIC_Write(0x4C, 0x01), //Set to Fixed EQ
DP159_IIC_Write(0x33, 0xF0), //Load EQ settings
DP159_IIC_Write(0x10, 0xF0), //Disable all Tx Lanes
DP159_IIC_Write(0x30, 0xE0), //Enable Rx Lane 0 only
printf("DP159 Re-Initialization has finished\r\r\r\n");
}
void BW_handler (void) {
u8 rtxen;
u8 eqreg;
u8 tsten;
u16 eq_lev = 8;
u32 link_bw;
u32 lane_count;
link_bw=DPSINK_IIC_Read(DPCD_LINK_BW_SET) & 0x0ff;
lane_count=DPSINK_IIC_Read(DPCD_LANE_COUNT_SET) & 0x0f;
rtxen = (lane_count == 1) ? 0xE1 : (lane_count == 2) ? 0xC3 : 0x0F;
eqreg = ((link_bw == 0x14) ? 0x0 : (link_bw == 0x0A ) ? 0x1 : 0x2 )<< 4 | (eq_lev & 0x0F);
tsten = (lane_count == 1) ? 0x11 : (lane_count == 2) ? 0x31 : 0xF1;
DP159_IIC_Write(0x10, 0xF0); // Disable TX lanes
DP159_IIC_Write(0x00, 0x02); // Enable Bandgap, Disable PLL, clear A_LOCK_OVR
DP159_IIC_Write(0x01, 0x01); // CP_EN = PLL (reference) mode
DP159_IIC_Write(0x0B, 0x33); // Set PLL loop filter
DP159_IIC_Write(0x02, 0x3F); // Set CP_CURRENT
DP159_IIC_Write(0x30, rtxen); // Enable RX lanes
DP159_IIC_Write(0x00, 0x03); // Enable Bandgap, Enable PLL, clear A_LOCK_OVR
DP159_IIC_Write(0x4C, 0x01); // Enable fixed EQ (use fixed when RX disabled)
DP159_IIC_Write(0x4D, eqreg); // Set EQFTC and EQLEV (fixed EQ)
}
int Dp159_reset(void)
{
int Status;
//=============================================
//Init PS GPIO module
//=============================================
Status=PSGPIO_Init(XPAR_PS7_GPIO_0_DEVICE_ID);
if (Status == 0) {
print("PS GPIO module initial PASSED\r\r\r\n");
}
else {
print("PS GPIO module initial FAILED\r\r\r\n");
}
//=============================================
//reset Dp159
//=============================================
set_gpio_value(MIO52, 0x0);//NC2
delay_nms(10);
set_gpio_value(MIO52, 0x1);//remove dp159 reset
//=============================================
//Init PS IIC module
//=============================================
Status = PSIIC0_Init(XPAR_PS7_I2C_0_DEVICE_ID);
if (Status == 0) {
print("PS IIC0 module initial PASSED\r\r\r\n");
}
else {
print("PS IIC0 module initial FAILED\r\r\r\n");
}
return Status;
}
////////////////////////////////////////////////////////
// main()
//
//
//
////////////////////////////////////////////////////////
void main( void )
{
u32 Status;
u32 uc;
UINT32 status = 0;
int i;
int test_num;
int test_base;
int rx_intr,rx_intr_new;
int power_mode;
u32 intrpt_value;
u32 unplug;
u32 tp1_intrpt;
u32 tp23_intrpt;
u32 tran_done;
u32 lost_tran;
u32 link_bw;
u32 lane_count;
u32 train_patrn;//DPCD TRAINING PATTERN SET,bit[1:0],00-traning off,01--Training pattern 1,
//10--Training pattern 2,11--Training pattern 3(DP1.2 standard)
ps7_init_linkwind();
Dp159_reset();
InitIt_Dp159();
dump_ip_info();
policy_maker_init();
dump_video_info();
uc=DPSINK_IIC_Read(SINK_DEV_COUNT);
xil_printf("SINK_DEV_COUNT is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(CDR_CONTROL_CONFIG);
xil_printf("CDR_CONTROL_CONFIG is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(LOCAL_EDID_VIDEO);
xil_printf("LOCAL_EDID_VIDEO is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(LOCAL_EDID_AUDIO);
xil_printf("LOCAL_EDID_AUDIO is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(GT_DRP_CHANNEL_STATUS);
xil_printf("GT_DRP_CHANNEL_STATUS is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(PHY_CONFIG);
xil_printf("PHY_CONFIG is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(PHY_POWER_DOWN);
xil_printf("PHY_POWER_DOWN is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(PHY_STATUS);
xil_printf("PHY_STATUS is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(AUX_REQUEST_IN_PROGRESS);
xil_printf("AUX_REQUEST_IN_PROGRESS is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(REQUEST_ERROR_COUNT);
xil_printf("REQUEST_ERROR_COUNT is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(USER_FIFO_OVERFLOW);
xil_printf("USER_FIFO_OVERFLOW is: 0x%x\r\r\n", uc);\
uc=DPSINK_IIC_Read(VIDEO_UNSUPPORTED);
xil_printf("VIDEO_UNSUPPORTED is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(AUDIO_UNSUPPORTED);
xil_printf("AUDIO_UNSUPPORTED is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(INTERRUPT_CAUSE);
xil_printf("INTERRUPT_CAUSE is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_LINK_BW_SET);
xil_printf("DPCD_LINK_BW_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_LANE_COUNT_SET);
xil_printf("DPCD_LANE_COUNT_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_PATTERN_SET);
xil_printf("DPCD_TRAINING_PATTERN_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_ENHANCED_FRAME_EN);
xil_printf("DPCD_ENHANCED_FRAME_EN is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_SCRAMBLING_DISABLE);
xil_printf("DPCD_SCRAMBLING_DISABLE is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_LINK_QUALITY_PATTERN_SET);
xil_printf("DPCD_LINK_QUALITY_PATTERN_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_RECOVERED_CLOCK_OUT_EN);
xil_printf("DPCD_RECOVERED_CLOCK_OUT_EN is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_SYMBOL_ERROR_COUNT_SELECT);
xil_printf("DPCD_SYMBOL_ERROR_COUNT_SELECT is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_LANE_0_SET);
xil_printf("DPCD_TRAINING_LANE_0_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_LANE_1_SET);
xil_printf("DPCD_TRAINING_LANE_1_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_LANE_2_SET);
xil_printf("DPCD_TRAINING_LANE_2_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_LANE_3_SET);
xil_printf("DPCD_TRAINING_LANE_3_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_DOWNSPREAD_CONTROL);
xil_printf("DPCD_DOWNSPREAD_CONTROL is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_MAIN_LINK_CHANNEL_CODING_SET);
xil_printf("DPCD_MAIN_LINK_CHANNEL_CODING_SET is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_SET_POWER_STATE);
xil_printf("DPCD_SET_POWER_STATE is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_LANE01_STATUS);
xil_printf("DPCD_LANE01_STATUS is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_LANE23_STATUS);
xil_printf("DPCD_LANE23_STATUS is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(SOURCE_OUI_VALUE);
xil_printf("SOURCE_OUI_VALUE is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(SYM_ERR_CNT01);
xil_printf("SYM_ERR_CNT01 is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(SYM_ERR_CNT23);
xil_printf("SYM_ERR_CNT23 is: 0x%x\r\r\n", uc);
uc=DPSINK_IIC_Read(DPCD_TRAINING_PATTERN_SET);
xil_printf("DPCD_TRAINING_PATTERN_SET is: 0x%x\r\r\n", uc);
while (1)
{
link_bw=DPSINK_IIC_Read(DPCD_LINK_BW_SET);
lane_count=DPSINK_IIC_Read(DPCD_LANE_COUNT_SET);
intrpt_value=DPSINK_IIC_Read(INTERRUPT_CAUSE);
train_patrn = DPSINK_IIC_Read(DPCD_TRAINING_PATTERN_SET);
xil_printf("DPCD_LINK_BW_SET is: 0x%x\r\r\n", link_bw);
xil_printf("DPCD_LANE_COUNT_SET is: 0x%x\r\r\n", lane_count);
xil_printf("DPCD_LINK_TRAIN_PATRN_SET is: 0x%x\r\r\n", train_patrn);
xil_printf("INTERRUPT CAUSE is: 0x%x\r\r\n", intrpt_value);
// uc=DPSINK_IIC_Read(DPCD_SET_POWER_STATE);
// xil_printf("DPCD_SET_POWER_STATE is: 0x%x\r\r\n",uc);
tran_done = intrpt_value & 0x04000;
lost_tran = intrpt_value & 0x10;
unplug = intrpt_value & 0x80000000;
tp1_intrpt = intrpt_value & 0x10000;
tp23_intrpt = intrpt_value & 0x60000;
if(tp1_intrpt==0x10000)
{
Tp1_Intr_Handler(link_bw, lane_count);
xil_printf("Current interrupt is Training pattern 1.\r\r\n");
}
else if(tp23_intrpt != 0x0)
{
Tp23_Intr_Handler();
xil_printf("Current interrupt is Training pattern 2 or Training pattern 3.\r\r\n");
}
else if (tran_done==0x4000)
{
xil_printf("training success.\r\r\n");
}
else if(unplug==0x80000000)
{
ReInitIt_Dp159();
DPSINK_IIC_Write(LINK_ENABLE, 0x00);
delay_nms(10);
DPSINK_IIC_Write(LINK_ENABLE, 0x01);
xil_printf("Cable is disconnect or unplug.\r\r\n");
}
else if(lost_tran==0x10)
{
DPSINK_IIC_Write(LINK_ENABLE, 0x00);
delay_nms(10);
DPSINK_IIC_Write(LINK_ENABLE, 0x01);
xil_printf("training is lost.\r\r\n");
}
}
}
