SN65LVDT386DGGR SI analysis

manu mohan

I have used SN65LVDT386DGGR as a receiver from multiple planks and that high speed signals routed to FPGA from the output of same chip.

Signals are operated in 75MHz and while I am tried to simulate the signals I have seen the signal from the driver side and receiver side waveform was not an expected pattern.

I have given 50% duty cycle in the simulator.I have used hyperlynx 9.2 version for the analysis.

I want to know ibis i chose is correct or not.

I have attached the waveform and ibis model.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/1373.0317.SN65LVDT386DGG.7z

over 9 years ago

0 Elias Villegas M. over 9 years ago

TI__Guru* 76130 points

Moving to high speed interface forum.

0 manu mohan over 9 years ago in reply to Elias Villegas M.

Intellectual 410 points

Hi,

Anyone have updated regrading above query ?

0 Michael Lu (Santa Clara) over 9 years ago in reply to manu mohan

TI__Mastermind 29655 points

Moving to Consumer & Computing Interface Forum for better support.

0 manu mohan over 9 years ago in reply to Michael Lu (Santa Clara)

Intellectual 410 points

There is any solution for above query ?

0 Elias Villegas M. over 9 years ago in reply to manu mohan

TI__Guru* 76130 points

Hello,
We are going to review the ibis file and provide feedback.
Regards

0 manu mohan over 9 years ago in reply to Elias Villegas M.

Intellectual 410 points

Thank you...

I am waiting for your review result.

Please let me know the details once you get the issue.

0 manu mohan over 9 years ago in reply to Elias Villegas M.

Intellectual 410 points

Hi,

Do you have any update ?

0 Elias Villegas M. over 9 years ago in reply to manu mohan

TI__Guru* 76130 points

Hello,
Sorry for the delay, I am pinging again the engineer responsible of the ibis model.
Regards

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SN65LVDT386DGGR SI analysis