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How to improvement eye pattern of DS92LV18

Satoshi
Guru 19645 points
Other Parts Discussed in Thread: DS92LV18

Customer evaluating DS92LV18, but eye pattern is not clear.

Layout and eye pattern(waveform) is attached.

Please let me know the possible causes.

I think that one of cause is long Length of connector⇔Device（20cm）

Are there other causes?

BLVDS.pptx

Below point are no problem, is it correct?

①Oscillation source(DC/DC, Clock IC, coil, etc) is not near device and line

②10-Layer (with solid GND)

③Bypass capasitor is close to supply pins

Best regards,

Satoshi

  • 0
    TI__Mastermind 29655 points
    Hi Satoshi-san,

    I do not expect the signal to be very clean at the Rx test point due to interconnect jitter that can possibly come from the connector and the board trace, as you have noted above. However, as long as the amount of jitter at the Rx input is less than the maximum total interconnect jitter budget (tJI) specified in the datasheet. To help us understand this case better, can you ask your customer to do the following:

    1. Can they take a similar scopeshot as you provided, but at the RJ-45 connector? I am interested to see the signal quality at the RJ-45 connector before the 20 cm of trace.
    2. Is the scope able to measure the jitter present on the measured waveform?
    3. Even though the signal quality does not look good at the Rx input, is the DS92LV18 still able to achieve lock?

    I agree with the points that you make about factors that sometimes affect signal integrity. They do not appear to interfere with the differential signals here.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Guru 19645 points

    Michael-san

    Thank you for reply.

    I checked below points.

    -------------------------------------------------------------

    1. Can they take a similar scopeshot as you provided, but at the RJ-45 connector?

    【Answer：Customer said that back layer's waveform is equal to near the connector, is it correct?】

    2. Is the scope able to measure the jitter present on the measured waveform?

    【Answer：Customer have to try】

    3. Even though the signal quality does not look good at the Rx input, is the DS92LV18 still able to achieve lock?

    【Answer：Lock-pin was locked(Low)】

    -------------------------------------------------------------

    Additional information is attached, schematic has been added.

    BLVDS2.pptx

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    TI__Mastermind 43795 points

    Hi Satoshi-san,

    I do not know what you are using to achieve loopback at the RJ45 connector.  It is very possible it is interfering with the signal quality.  Have you tried to remove the RJ45 connector and connect the Rin and Dout signals with very short pieces of wire?

    Regards,

    Lee