• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 1080 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS125DF410 - Device operation after CDR Reset

Kawai
Guru 19785 points
Other Parts Discussed in Thread: DS125DF410

Hello Team,

Could you please allow me to confirm my recognition of DS125DF410 after resetting the CDR with REG 0x0A ?

I believe the device re-starts scanning the input frequency (data rate) by sweeping VCO frequency from 9.8Gbps to 12.5Gbps (full VCO range) including divided frequency range (subrate). Then, compares input data rate and PPM count/PPM count tolerance. If it meets the PPM count and PPM count tolerance, the device will judge as LOCKed. Am I correct ?

CDR reset is done through following register settings. (REFMODE is default setting.)

1). ADR 0x0a = 0x1C      // CDR Reset　assert
2). ADR 0x0a = 0x18 or 0x10      // CDR Reset de-assert

Best Regards,

Kawai

  • 0
    TI__Mastermind 19235 points

    Hi Kawai. Your statement is fair though I'd like to clarify one point.

    The default CDR reference mode for DS125DF410 is ref_mode 3. In ref_mode 3 the retimer expects an Input reference clock  to run the PPM counter. In addition, for ref_mode 3 the expected data rate must be programmed into the CDR either through the rate/sub-rate table (i.e. channel register 0x2F) or entered manually via registers 0x60 to 0x64 with the corrected divider settings. The PPM counter constrains the allowable lock ranges of the CDR according to the programmed values in the rate/sub-rate table or the manually entered data rates. Thus, you don't actually sweep through the entire VCO frequency range when in ref_mode 3. This allows you to achieve a faster lock time, in the order of tens of milliseconds.

    Regards,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Guru 19785 points
    Hello Rodrigo-san,

    Please allow me to confirm with an example.

    [Q1]
    In Ref_Mode 3, let's say that customer had programmed to manual based mode, 5.5Gbps with PPM Tolerance with 1000ppm. In this case, does the device only scan the VCO frequency of 11GHz with some plus/minus window ?
    I was thinking that Ref_Mode 3 also scanned all the VCO frequency as register description statement had "all capdac".

    [Q2]
    I believe when assert -> de-ssert CDR reset, VCO calibration would occur which optimizes the best VCO setting inside the device, something similar with LMK03xxx/04xxx devices. Am I correct ?

    [Q3]
    To scan the all supported VCO frequency range, should you use Ref_Mode 0 ?
    In this case, I understand lock time would be very long, could be 1sec or longer.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 19235 points

    Hi Kawai-san, see below.

    [Q1]
    In Ref_Mode 3, let's say that customer had programmed to manual based mode, 5.5Gbps with PPM Tolerance with 1000ppm. In this case, does the device only scan the VCO frequency of 11GHz with some plus/minus window ?
     

    Correct

    [Q2]
    I believe when assert -> de-ssert CDR reset, VCO calibration would occur which optimizes the best VCO setting inside the device, something similar with LMK03xxx/04xxx devices. Am I correct ?

    When CDR reset is applied, you re-trigger both CDR lock process and EQ adaptation process.


    [Q3] To scan the all supported VCO frequency range, should you use Ref_Mode 0 ? In this case, I understand lock time would be very long, could be 1sec or longer.


    Correct, that is what ref_mode 0 does. ANd indeed the CDR lock time is extended to around 1 second.

  • 0 in reply to Rodrigo Natal
    Guru 19785 points
    Hello Rodrigo-san,

    Thank you for the answers.

    Please allow me to confirm a little more about Q2.

    I believe when the device is unlocked, CDR re-lock process and EQ adaptation process would start. AM I correct ?

    I am asking this because after programming the registers, the device were repeating LOCK and UNLOCK to the input signal. However, it would correctly LOCK to the input signal after CDR reset. What would be the difference between LOCK->UNLOCK process and CDR reset ?

    *We are understanding that CDR Reset is required after any register changes, but, it would be helpful if we could have any opinion.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Mastermind 19235 points

    Hi Kawai-san. The retimer will initilaize the CDR lock/EQ adaption process during the following conditions:

    • Upon VDD power-up
    • Upon CDR reset and releaase
    • Upon significant change in input signal, such as data off-on, which results in CDR losing lock

    Regards,

    Rodrigo Natal