DS90CR481,DS90CR482 LVDS clock signal

Hi,

Can you provide more details about your question? I have noted in the datasheet on p. 13 that "The Deskew feature operates up to clock rates of 80 MHz only." This may be why something does not quite appear correct on the LVDS clock. Does this feature work on a lower data rate?

Michael

Ｔｈａnks relply, y'll welcome.

I'm not mentioned receiver "Deskew" , just about transmitter. Or Datasheet say BAL operates up to clock rate of 80MHz?

LVDS clock signal  seems "11110000" and "111000" , It  would be "11110000111000" or "00001110001111" so , each 7clocks of  "1-0" signal  transition

occurs... other word "falling-edge"?

Hi,

If you choose to use the DS_OPT pin on the transmitter, then this implies that you are attempting to perform deskew calibration, since the DS_OPT pin (when pulled high) initiates the deskew calibration pattern. According to the datasheet, this feature is only applicable for clock frequencies up to 80 MHz.

DC balancing (BAL) works across all operable frequencies.

I am not sure I understand your second question. To help me understand what is happening, can you share some oscilloscope waveforms of the LVDS clock and data when DS_OPT = High and DS_OPT = Low, so we can analyze what you are seeing? More specifically, can you measure the amount of time per period where the LVDS clock signal is high? 

Thanks,

Michael

Hi Michael, you'll welcome anytime.

Oh, I've only  the waveform LVDS clock signal at case DS_OPT = High.

It is intend to that 'Transmitting with no use deskew , use DC balancing @ clock in is 100MHz' .

so DS_OPT = are fixed 'High' all time.

 

So, When I get eye-pattern of the data signal, I have to trigger to falling-edge of LVDS clock.

And make recovered-clock 7 times. 

Hi,

I looked at the waveform, and the waveform seems quite noisy.

I am wondering if the waveform is a valid test case, since you are not planning to use the Deskew feature and only need DC balancing. If this is the case, then DS_OPT should be held low all the time (or left open, so the internal pull-down resistor will keep the pin low), not high all the time. I think in your current situation, the DS90CR481 will attempt to implement the beginning of the deskew procedure, but if it is held high all the time, the deskew process will not complete. Moreover, this deskew procedure, as mentioned previously, is only supported up to 80 MHz.

Are you seeing system issues with your current setting with DS_OPT = High at 100 MHz because of this behavior? If so, what kind of problems are occurring in the overall system?

Regards,

Michael