My customer is running into an issue during USBC enumeration, specifically power negotiation. Here is a bit of context regarding their implementation. I can send the .CTB files over email if necessary:
"We have two boards communicating over USBC. One of these boards will always be both the USB host and the power source of the pair. The other will always be the slave/power sink. We have added a single PDO for both the source and the sink on top of the default 5V@2A profile. I've captured the TI Config tool's PDO settings and attached them to this email. Please let us know if there is anything you'd like us to try.
The issue we are having right now is that the host TPS chip seems to be continually resetting our slave device during enumeration, and our theory is that it is doing this right after PDO negotiation. Watching VBUS on a scope reveals that the reset cycle consists of an initial voltage of 5V, a brief jump to our intended voltage of ~12.3v, and then an immediate drop to 0v before the cycle restarts by assuming a 5v level.
What complicates this issue for us is that these same .ctb files and the very same host device are capable of successfully negotiating VBUS on a previous HW iteration of our slave device. If I remove PDO1 from our current slave device's configuration, then the host will successfully provide us with a 5v VBUS which allows for most of our slave device's HW features to be validated as functional. Because of this we're hesitant to believe an electrical short exists on our slave board which could be causing a protection scenario on our host.
If you have any suggestions for changes to be made to our .ctb files or additional questions about our implementation please let me know.
As for us, we would like to know about what debugging tools exist that we could put to use for proving out our implementation, and whether or not you would be able to help us gain temporary access to them to get through this issue."
