Trouble with SN65LVDS310

Thanks for the reply.

1/ The CM voltage on the input signals is around 850mV (see the scope screenshot above for more detail)

2/ Schematic details below.

FPGA first, where we have a full bank dedicated for these output signals (so we can play with voltage levels)

Please note that these cap footprints have been fitted with 470ohm resistors.

Schematic of the SN65LVDS310:

Any comments/questions/suggestions welcome.

Diego,

Indeed, we have 4 boards at our disposal; all show the same behaviour.

One more element: the waveforms above were probed on the resistors close at the FPGA, so before the 3cm 'transmission line'. We cannot probe the signal close to the receiver. But with a 4MHz clock running over 3cm, I believe this should not be an issue.

Is it correct that the state of the datalines have no influence at all on the generation of the output clock? Even though they carry signals of the same voltage levels as the input clock, the data probably fails the CRC check.

Riemerg, I took a quick look.  It's not clear what the problem is.  One thing you could check is Icc: does it match active, standby, or shutdown mode?  Does disabling the clock have no effect on Icc?

Next, can you increase the clock VID or its frequency to see if that fixes it?  I think you can exceed 200mV without problem.

Best regards,

RE

RE,

Thanks a lot for your reply and suggestions.

1/ Voltage level

We've tried applying larger voltage swings, but the result stays the same. We even went to 1Vpp, so 2Vpp differential. The measurements below were done with resistors resulting in 260mVpp differential, so 130mVpp single-ended, on a 850mV common mode.

2/ Frequency - Current

Unfortunately, the PCB allows us only to measure global current consumption.

Below the combined current consumption based on some clock variations:

Clock off (both entries at 1.8V): 0.986mA

4.125MHz clock: 2.529mA

6.667MHz clock: 2.533mA

10.000MHz: 2.538mA

Looking at a shutdown spec of 0.01mA and standby spec of 0.1mA, it seems the chip is in Acquire or Receive mode. Not sure which one of them?

3/ PCLK output pin

When we first power the device and leave the clock inputs floating, the device presents a 46.6mV voltage on the PCLK pin. As soon as we start driving the input clock, the PCLK seems to be forced to 0V.

Of course, any other suggestions/thoughts are very welcome!

We have the opportunity of a respin of the same board beginning of next week, so feedback is very much appreciated.

Regarding 3/ PCLK output pin:

The PCLK pin (as well as all other connected output pins of the SN65LVDS310 in the schematics above) is looped back to the FPGA. Hence, the 46.6mV will probably be caused by the pull-up of the FPGA when it's unconfigured. Once configured, the FPGA floats all of the SN65LVDS310 outputs.

So we're not sure the SN65LVDS310 is really changing the state of PCLK when presented with a clock.

However, the PCLK is low, while its other outputs are high, while all of them are treated the same (floated) by the FPGA.

Hi riemerg,

Can you try toggling RXEN to see if that changes current by 0.015mA?  That's the difference between standby and shutdown mode (per the datasheet).

Quite simply, "A high input signal on RXEN combined with a CLK input signal switching faster than 3 MHz and VICM smaller than 1.3 V forces the SN65LVDS310 into the active mode."  If there is no PCLK output, then something unexpected is wrong.  Check connections, and verify the schematic.

Best regards,
RE

With this issue still not being solved, we received support from TI by mail, so I list the communication below to keep this thread updated:

The only issue I can imagine is  soldering issue or improper connection of the pins and GND.

Dear TI engineers,

This might be the last post in this thread. If it it not possible to provide us with an evaluation module, or at the very least with a screencapture of the input waveforms of a working setup, we will be forced to use an alternative part from a different vendor. At this point, this chip is the only remaining hardware issue we have on this project.

Regards,

Riemer

Elias,

Thanks for the offer, I hadn't yet though about this opposite approach approach, but it could obviously work as well.

Would it be possible to contact me at riemer (dot) grootjans (at) gmail (dot) com? Afterwards I will contact you through my working mail to discuss the practical details.

Regards,

Riemer

Dear TI engineers,

Would it be possible to provide a short answer? The functionality of our current design is severely limited because of this issue.

Regards,

Riemer

Dear TI engineers,

Any update please?

Regards,

Riemer

Elias,

Thank you for the reply.

That is correct; we have a board ready to be shipped to you once we get the shipping address. Please contact me on the mail address I provided earlier, so I can already share all details about the board.

Regards,

Riemer

Elias,

I haven't yet received a mail from you.

Please send a message to riemer (dot) grootjans (at) gmail (dot) com, after which I will contact you from my working mail in order to get the board to you asap.

Regards,

Riemer

Elias,

Can you please give me an update regarding how to get to a solution? I have far too many positive experiences with TI to give up on a chip like this. All I'm asking is to send me a mail, so I can share all details regarding the non-working 307+310 combination we have. Preferably an address as well, so we can look at the same type of board.

Regards,

Riemer

Hello,

Sorry for the long delay, at this moment it will be impractical to receive your board.

We talked with the Tech champion and this is what we think is going on:

They attenuation is such that the common mode below 0.9 X VDD LVDS

 It will put the device into standby mode and kill the output.

Elias,

Apologies for the delayed answer, in the meantime we asked for and received a FIN424/FIN425 ser/deser devkit from Fairchild which is working quite fine.

However, since our current protos have the SN65LVDS310 implemented and this is a better (smaller) fit for our smartglass , I would still very much prefer to get this IC working.

That being said, can you please ask your tech expert to have a quick look at my original post, where you can clearly see the common mode is at 850mV, which is well below 0.9*VDD = 1.62V.

At this moment, I'm thinking we're dealing with bad silicon (even though these parts originated from Digikey). Is there a way you could get validated silicon to us fast? So we can replace the component on the boards. I would like to check this asap, as we'll need to make the call between FIN425 and SN65LVDS310 soon (redesign is currently planned next week).

Regards,

Riemer