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TMDS361B Function of the clock-detect circuit

na na78
Guru 16770 points
Other Parts Discussed in Thread: TMDS361B

Hi

We want to find the following information.
If you have the answer, could you show us?

Device:TMDS361B
1. Do you have the impedance value for following inputs? (Pin 4, 5, 38 39, 53, 54 TMDS_CLK input)

2. What is the TMDS input clock-detect circuit?
We are looking for the information about input clock-detect circuit. How does it determine the presence or absence of the clock?

Best regards

  • 0
    TI__Mastermind 23815 points
    Hi,

    HDMI uses TMDS for data lanes and clock lane, all of them have 50ohm pullups to Vcc on each signal of differential pair. you can see this in DS page 7.

    Clock signals should meet minimum amplitude and frequency thresholds, refer to DS figure 13.

    Regards
  • 0 in reply to Moises Garcia
    Guru 16770 points
    Hi Moises

    Thank you for your information.

    Best regards
  • 0 in reply to na na78
    Guru 16770 points

    Hi Moises

    We have additional questions.

    1. tCLK1 (typ:300ns , max:500ns) and tCLK2 (typ:500ns, max:800ns) are defined in the following conditions.

    tCLK1 : AVCC=3.3V, Rt=50ohm, Input TMDS clock frequency = 300MHz
    tCLK2 : AVCC=3.3V, Rt=50ohm, Input TMDS clock frequency = 1MHz

    Does it means tCLK1 and tCLK2 depends on input TMDS clock?

    2. Even If the TMDS clock frequency = 25MHz, the spec of tCLK1 (typ:300ns , max:500ns) and tCLK2 (typ:500ns, max:800ns) can be applied?

    3. Is the function of Clock-detection working during the period of tCLK2?


    Best regards

  • 0 in reply to na na78
    TI__Mastermind 23815 points

    Hi,

    Clock detect is working all the time,

    tCLK1 is the time it takes to detect a valid clock, a clock from 25MHz to 300MHz, as example the measurement was made with the highest valid clock(300MHz).

    tCLK2 is the time it takes to detect an invalid clock, as example the measurement was made with a 1MHz clock.


    The time it takes to detect a valid clock, could depend on clk frequency, but always within tCLK1 range.

    Regards

  • 0 in reply to Moises Garcia
    Guru 16770 points
    Hi Moises

    Thank you.
    We understood your reply.

    We have found that the unwanted noise which has about 150mV voltage level is flowed into the clock line,
    and it seems to result in unexpected behavior of power-management function.

    We think reducing the noise is the best way.

    Normally, what do you think the cause of such noise on input clock line for TMDS?
    Do you have idea?

    We appreciate your help.

    Best Regards
  • 0 in reply to na na78
    TI__Mastermind 23815 points
    Hi,

    It depends on the frequency of the signal, it may come from crystals, oscillators, other communications interfaces, in depends on your applications.

    Regards