• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 791 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB928 PLL is unlocked intermittently

Daisuke Maeda
Guru 20205 points
Other Parts Discussed in Thread: DS90UB928Q, DS30EA101

Our customer often sees that the LOCK status output signal is driven low intermittently after FPD-Link III serial cable was reconnected.

Their system which is powered up after the serial cable was connected tight works fine. Then the error often occurs if reconnected after the serial cable was loosened or removed.

Why does the error occur? How can the error be removed?

Best regards,

Daisuke

  • 0
    Guru 20205 points

    Hi,

    Can the FPD-Link III serial cable be removed and reconnected after power on?

    Is the reset by the Power-down Mode Input Pin (PDB) required after reconnected?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    Guru 20205 points

    Hi,

    Our customer uses DS30EA101 with DS90UB928Q. The DS30EA101 differential output is automatically disabled (to a logic 1) by LOS and EN being tied together when no input signal is present. Therefore ±450mV (Max) continues being applied to DS90UB928Q differential input while the serial cable is removed.

    Does this condition have a problem?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    Guru 20205 points

    Hi,

    Daisuke Maeda said:

    Our customer uses DS30EA101 with DS90UB928Q. The DS30EA101 differential output is automatically disabled (to a logic 1) by LOS and EN being tied together when no input signal is present. Therefore ±450mV (Max) continues being applied to DS90UB928Q differential input while the serial cable is removed.

    Does this condition have a problem?

    Our customer checked the logic level at LOS and EN being tied together, then it is always low regardless of whether the serial cable is connected.

    Why is LOS driven low when the serial cable is unconnected?

    I think the unsettled signal continues being applied to DS90UB928Q differential input while the serial cable is unconnected.

    Does this condition have a problem?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    Guru 20205 points

    Hi,

    DS90UB928Q datasheet describes:

    "When PDB is driven HIGH, the CDR PLL begins locking to the serial input and LOCK is TRI-STATE or LOW
     (depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial
     data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available
     on the LVCMOS and LVDS outputs. "

    While PDB is HIGH, can the CDR PLL begin the lock sequence again after the CDR PLL is unlocked?

    If not so, I think that DS90UB928Q must be reset by PDB after the serial cable was reconnected. Is my thought correct?

    Best regards,

    Daisuke