This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90LV001 Aspect of tSKD1, tSKD3, tSKD4

Guru 16770 points
Other Parts Discussed in Thread: DS90LV001

Hi

Now, we refer DS90LV001 and we want to confirm the meaning of tSKD1, tSKD3 and tSKD4 with AC test circuits and timing diagrams.

According to the datasheet, AC Test Circuits and Timing Diagrams is described as Figure4 and Figure5.

The AC Test Circuits can be referred as it is.
However, we could not determine tSKD1, tSKD2 and tSKD4 in the timing diagrams.

So, our image is like following pictures.
tSKD1 means to make a bit period longer or shorter in same channel,  doesn't it?



Next, tSKD3 and tSKD4 are part to part skews.

Following pictures are our image.
We think tSKD3 and tSKD4 are the similar parameters as the tSKD1 but they have different conditions. Are they correct?

Best regards

  • Hi,

    Thanks for your patience and apologies for the slow response. We are looking into your question and will get back to you in the next few days.

    Regards,

    Michael
  • Hi 

    Your picture for TSKD1 is correct.  This specification is from the same device.  It does not apply to different devices.

    Your picture for TSKD3 and TSKD4 is correct.  It is important to understand that delays I and III must also meet TSKD1 and delays II and IV must also meet TSKD1.

    Regards,

    Lee

  • Hi Lee

    Thank you for your reply.

    Could you answer the following question?

    For a single device, are there specifications between differential input(In+ and In-)?

    If the differential inputs (IN+ / IN-) have a little skew like following, how does it affect to the output?

    Best Regards

  • Controlling the +\- relationship is important in differential systems.  When the single ended waveforms phase relationship strays from an ideal 180 degrees, some portion of the differential signal will be converted to a "common mode" signal.  This signal is easily radiated and can impact a systems ability to pass EMI/EMC testing.

    For the reason above differential drivers and differential traces are designed with a high degree of symmetry.  It is normal for some transmission line structures - like cables, connectors, and traces to exhibit some non-symmetrical behavior.  A good rule of thumb is to limit any skew between the +\- signals to less than the original transmitted edge rate.

    In the example above the DS90LV001 outputs will see some minor impact (skew = rise/fall time).  Increasing the +\- signal timing offset  further will eventually produce a non-monotonic differential signal at the DS90LV001 input which will likely result in duty cycle distortion and increased jitter at the device output.

    Regards,

    Lee 

  • Hi Lee

    Thank you for your info.

    I understood the input +\- skew should be less than the original transmitted edge rate.

    For confirmation, could you review if my understanding of the output skew is correct?

    Supposed tPHLD(min) is 1ns and tPLHD(max) is 2ns in the above figure.

    Even if +\- input has no skew, the differential outputs themselves are likely to have skew of the 1ns at most. Is this correct?

    Best regards

  • Hi,

    Actually all of the skew specifications are based off of Differential measurements.  The individual Out+ and Out- signals will have very low amounts of skew, typically < 25 ps.  If the inputs have no skew like you have shown in the figure above, the differential output will switch between 1.0 and 2.0 ns under all process, voltage, and temperature variations.

    When a device is operating at one voltage and temperature, the difference between TPLHD and TPHLD is much smaller. See TSKD1 where the maximum difference is 200 ps.

    Regards,

    Lee

  • Hi Lee

    Thank you for your reply.

    >The individual Out+ and Out- signals will have very low amounts of skew, typically < 25 ps
    Is this rule of thumb?

    Best regards
  • Yes the number is approximate.  The output circuit is designed to have Out+ and Out- switch at exactly the same time, but small non-ideal behavior will result in some small skew observations.

    Regards,

    Lee

  • Hi Lee

    In previous answer, you mentioned if the single ended waveform phase relationship strays from an ideal (in other words, "they have skew") some portion of the diff signal will be converted to a "common mode" signal.

    So, if there is skew between IN+\IN-, this doesn't impact as output skew?

    For example, 100ps skew between IN+\IN- is supposed.
    This 100ps skew doesn't come as OUT+\OUT- skew but comes as common mode signal, does it?
    (Consistently, Out+ and Out- signals will have low amounts of skew, typically < 25 ps whatever skew input has)

    Best Regards
  • Hi,

    IN+/IN- "intra-pair" skew will result in a common mode signal component on the DS90LV001 inputs.  This portion of the signal is rejected by the input differential amplifier.  However, the result of this type of skew on the input will be some measure of Duty cycle distortion of the differential signal at the outputs.

    The output skew between OUT+ and OUT- will not change.

    Regards,

    Lee 

  • Hi Lee

    Thank you for your help.
    We understood IN+/IN- "intra-pair" skew will cause Duty cycle distortion of the differential signal at the output.

    Anyway, "intra-pair" skew is proper representation in my question.

    So, OUT+\OUT- intra-pair skew is typically < 25 ps in DS90LV001 according to rule of thumb , right?

    Best regards
  • Yes, the DS90LV001 OUT+/OUT- intra-pair skew is typically < 25ps

    Regards,

    Lee

  • Hi Lee

    Thank you for your answer.

    Our questions are cleared . So, we finish this thread. Thanks.

    Best regards