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TLK105LRHBR - MLED Configuration issue

Chithambara Ganesh57
Intellectual 490 points
Other Parts Discussed in Thread: AM4379, TLK105

Hi,

We are using TLK105LRHBR for 100Mbps Ethernet in MII Mode. In that, We are using pin 29 of PHY (COL(MLED)/PHYAD0) for Blinking LED purpose. And we are using Generic Driver.

Processor used in design in AM4379.

From datasheet of TLK105, it is mentioned that,

"The MLED is not activated by
default, but by register access it can be routed through either pin 17 (allowing more configuration options
for pin 17), or pin 29 supporting two simultaneous LEDs (LED_LINK on pin 17 & MLED on pin 29)." and

"REG 0x0025 (MLEDCR Register) controls the MLED routing and configurations"

But we are not able to change 0x0025 register. By default PIN 29 is going LOW State. So, LED is glowing always. Is there any patch available?

  • 0
    TI__Mastermind 31600 points
    Could you clarify what you mean when you say you "are not able to change 0x0025 register"? Are you having difficulty with extended register access?

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 490 points
    Hi Patric,

    We are able to access extended register. We configured it for Blinking Functionality. But when i am doing UDHCPC from processor, pin 29 is going OFF only once at the initial time, then it is glowing ON continuously.

    Please explain why it is happening and how to overcome it.,

    Thanks,
    Ganesh.
  • 0 in reply to Chithambara Ganesh57
    TI__Mastermind 31600 points
    Ganesh,

    Could you please provide a register dump of the PHY during your UDHCPC testing so that we can check the configuration?

    Patrick
  • 0 in reply to Patrick OFarrell
    Intellectual 490 points
    Hi Patrick,

    Please find following logs to check the register dump,

    root@am437x-evm:~# udhcpc -i eth1
    udhcpc (v1.23.1) started
    [ 58.920392] net eth1: initializing cpsw version 1.15 (0)
    [ 59.003201] genphy_config_init: CR2 Read value = 0X104
    [ 59.008587] genphy_config_init: CR2 Read value = 0X104
    [ 59.015481] genphy_config_init: MLEDCR Read value = 0X0
    [ 59.021004] genphy_config_init: MLEDCR Read value = 0X400
    [ 59.027980] net eth1: phy found : id is : 0x2000a212
    [ 59.037128] 8021q: adding VLAN 0 to HW filter on device eth1
    [ 59.043644] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
    Sending discover...
    [ 62.023715] cpsw 4a100000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off
    [ 62.032107] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
    Sending discover...
    Sending select for 192.168.17.14...
    Lease of 192.168.17.14 obtained, lease time 172800
    /etc/udhcpc.d/50default: Adding DNS 192.168.10.50
    root@am437x-evm:~#

    Thanks,
    Ganesh.
  • 0 in reply to Chithambara Ganesh57
    Intellectual 490 points

    Hi,

    Any update for this issue,

  • 0 in reply to Chithambara Ganesh57
    Intellectual 490 points

    Hi TI Team,

    Can you please update here for debugging this issue ASAP. We are not able to complete deliverable to customer because of this issue.,

    Thanks,

    Ganesh.

  • 0 in reply to Chithambara Ganesh57
    TI__Mastermind 31600 points

    Ganesh,


    Sorry, I should have been clear about the specific registers that I want to see in the register dump.  Please dump out the contents of the following registers during your UDHCPC testing:

    1. Basic Mode Control Register (BMCR), address 0x0000
    2. Basic Mode Status Register (BMSR), address 0x0001
    3. Control register 1 (CR1), address 0x0009
    4. Control register 2 (CR2), address 0x000A
    5. Control register 3 (CR3), address 0x000B
    6. Fast Link Down Status (FLDS), address 0x000F
    7. PHY Status Register (PHYSTS), address 0x0010
    8. PHY Specific Control Register (PHYSCR), address 0x0011
    9. LED Control Register (LEDCR), address 0x0018
    10. PHY Control Register (PHYCR), address 0x0019
    11. Multi LED Control register (MLEDCR), address 0x0025

    I want to confirm both the LED configuration and the link configuration.  As before, please read each register twice and provide both values.

    Thanks,
    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 460 points
    There was a problem in writing 0x25 register. now its fine and working