LMH1983 User Defined Format to Genlock

Nobuyoshi Furihata

Other Parts Discussed in Thread: LMH1983

We have a recovered video clock that is divided from 148.5 MHz clock and resampled by 156.25 MHz network clock. We want LMH1983 in auto format detection to genlock to this clock.

At first, when we fed 14.85 MHz into the LMH1983 HIn, and GND to VIn and FIn, LMH1983 detected it as format code 29 (27 MHz Hsync) and PLL1 wasn’t locked. When we disabled auto format detection and forced user defined format, PLL1 was locked.

Next when we changed the frequency to 742 kHz, PLL1 never locked and the device status showed Wrong_Format although it detected the user defined format.

Our questions are:

What does Wrong_Format mean in user defined format ?
What frequency range and clock format is acceptable for HIn of LMH1983 user defined format ? Is the rage only within 6-67 kHz ?

regards,

Nobu Furihata

over 9 years ago

0 Nasser Mohammadi over 9 years ago

TI__Guru* 93670 points

Greetings Furihata-San,

1). LMH1983 counts clock pulses between HSYNC pulses and uses F and V sync to determine incoming video frame format. Valid video frames are listed in table 2 of the data sheet.

2). As you noted the range is within 67 KHz.

I would appreciate it if you could please let me know about this application and provide us with more details.

Regards,,nasser

0 Nobuyoshi Furihata over 9 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

Our product supports three types of source clock to genlock. They are video signals, audio word clock and network transferred AV clock. We use LMH1983 to genlock to video signals or word clock, and another PLL to genlock to the AV clock.

The AV clock is generated from 148.5 MHz clock and the divisor can be changed at this time. We want to use the user defined format to detect the AV clock and remove the PLL.

As there was another thread to use the user defined format to detect 192 kHz word clock, our idea to detect 742.5 kHz or so is not so bad.

Is this impossible for LMH1983 to do ?

Regards,

Nobu Furihata

0 Nasser Mohammadi over 9 years ago in reply to Nobuyoshi Furihata

TI__Guru* 93670 points

Hi Furihata,

I think it is possible.

You are going to apply 742.5KHz to HSYNC input. There is PLL1 R Divider register(0x29-0x2A) which divides down Hsync. You can set this register to 0x0B or 11 decimal. Then there is another register PLL1 N Divider(0x2B-0x2C) which divides down the PLL1 27MHz clock. Divided down version of 742.5KHz and 27MHz clocks should be the same to allow PLL1 to lock. PLL1 N Divider(0x2B-0x2C) should be set to 400 decimal or 0x192 hex to get these two clocks to be the same.

Given this, PLL1 should be genlocked to 742.5KHz incoming clock. After this change, you may need to fine tune loop bandwidth to make sure the loop is stable.

Regards,,nasser

0 Nobuyoshi Furihata over 9 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

PLL1 never locked to 742.5 kHz HIn clock, though LMH1983 detected the user defined format with your register combination. I don’t know why but the Wrong_Format bit is set in Device Status.

Status registers are as follows:

Reg 0x00 = 0x2C

Reg 0x01 = 0x60

Reg 0x02 = 0xE0

Reg 0x20 = 0x1F

Reg 0x21 = 0x08

Reg 0x28 = 0x05

Reg 0x29 = 0x00

Reg 0x2A = 0x0B

Reg 0x2B = 0x01

Reg 0x2C = 0x92

I tried with some values of PLL1 charge pump current, but never locked.

HVF input of LMH1983 is multiplexed by FPGA and video signals and 48kHz word clock are automatically detected and locked correctly.

The 742.5 kHz clock is generated from 148.5 MHz clock output of another LMH1983 locked to video. Then it is transferred via network and retimed by 156.25 MHz receive clock. This results 6.4 ns jitter (1344ns or 1350.4ns cycle clock).

My register settings are as follows:

Reg 51 = 0x02

Reg 52 = 0xDE

Reg 53 = 0x02

Reg 54 = 0xD0

Reg 55 = 0x00

Reg 56 = 0x0B

Reg 57 = 0x01

Reg 58 = 0x92

Reg 59 = 0x05

Reg 5A = 0x00

Reg 5B = 0x01

Reg 5C = 0x00

Reg 5D = 0x88

Do you have any suggestions to go forward ?

Regards,

Nobu Furihata

0 Nasser Mohammadi over 9 years ago in reply to Nobuyoshi Furihata

TI__Guru* 93670 points

Hi Furihata,

Could you please send us your LMH1983 register dump from Reg 0x00 to 0x5D.

Regards,,nasser

0 Nobuyoshi Furihata over 9 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

Here is my LMH1983 register dump.

Reg 0 = 0x2C
Reg 1 = 0x60
Reg 2 = 0xE0
Reg 3 = 0xC0
Reg 4 = 0x00
Reg 5 = 0x2B
Reg 6 = 0x08
Reg 7 = 0x0E
Reg 8 = 0x0D
Reg 9 = 0x00
Reg A = 0x0F
Reg B = 0x00
Reg C = 0x00
Reg D = 0x00
Reg E = 0x00
Reg F = 0x00
Reg 10 = 0x00
Reg 11 = 0x34
Reg 12 = 0x30
Reg 13 = 0x30
Reg 14 = 0x30
Reg 15 = 0x02
Reg 16 = 0x03
Reg 17 = 0xFF
Reg 18 = 0x01
Reg 19 = 0xFF
Reg 1A = 0x00
Reg 1B = 0x01
Reg 1C = 0x10
Reg 1D = 0x00
Reg 1E = 0x00
Reg 1F = 0x00
Reg 20 = 0x1F
Reg 21 = 0x08
Reg 22 = 0x05
Reg 23 = 0x06
Reg 24 = 0x00
Reg 25 = 0x01
Reg 26 = 0x00
Reg 27 = 0x1F
Reg 28 = 0x05
Reg 29 = 0x00
Reg 2A = 0x0B
Reg 2B = 0x01
Reg 2C = 0x92
Reg 2D = 0x08
Reg 2E = 0x00
Reg 2F = 0x02
Reg 30 = 0x0C
Reg 31 = 0x00
Reg 32 = 0x03
Reg 33 = 0x05
Reg 34 = 0x20
Reg 35 = 0x08
Reg 36 = 0x4B
Reg 37 = 0x02
Reg 38 = 0x00
Reg 39 = 0x16
Reg 3A = 0x49
Reg 3B = 0x00
Reg 3C = 0x01
Reg 3D = 0x0A
Reg 3E = 0x50
Reg 3F = 0x04
Reg 40 = 0x65
Reg 41 = 0x00
Reg 42 = 0x01
Reg 43 = 0x08
Reg 44 = 0x98
Reg 45 = 0x04
Reg 46 = 0x65
Reg 47 = 0x00
Reg 48 = 0x01
Reg 49 = 0x00
Reg 4A = 0x0B
Reg 4B = 0x00
Reg 4C = 0x00
Reg 4D = 0x00
Reg 4E = 0x00
Reg 4F = 0x00
Reg 50 = 0x00
Reg 51 = 0x02
Reg 52 = 0xDE
Reg 53 = 0x02
Reg 54 = 0xD0
Reg 55 = 0x00
Reg 56 = 0x0B
Reg 57 = 0x01
Reg 58 = 0x92
Reg 59 = 0x05
Reg 5A = 0x00
Reg 5B = 0x01
Reg 5C = 0x00
Reg 5D = 0x88

Regards,

Nobu Furihata

0 Nasser Mohammadi over 9 years ago in reply to Nobuyoshi Furihata

TI__Guru* 93670 points

Hi Furihata,
I am working on this and will have comments within the next couple of days.
Regards,,nasser

0 Nasser Mohammadi over 9 years ago in reply to Nasser Mohammadi

TI__Guru* 93670 points

Hi Furihata,

I generated 742.5KHz clock and used with LMH1983EVM. I was able to get PLL1 to lock to this clock. Please attached note LMH1983 register settings to enable genlock to this clock in custom mode. In these settings, we are enabling custom mode and over-write registers 0x51 through 0x5D. I Also, EN_AFD needs to be disabled. Also, i multiplied R1 and N1 dividers by 4. Please try these and let me know.

I would appreciate if you could please tell me about the company you work for and a bit more about this application. If you prefer, please send me email at nasser.mohammadi@https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/742p5KHz-Custom-Mode-Setting-1.nrdti.com

Regards,,nasser

0 Nobuyoshi Furihata over 9 years ago in reply to Nasser Mohammadi

Prodigy 50 points

Hi Nasser,

Thank you for your support.

I changed over-write registers and disabled AFD as your note, but the situation was not changed.

Here is my LMH1983 register dump.

Reg 0 = 0x2C
Reg 1 = 0x60
Reg 2 = 0xE0
Reg 3 = 0xC0
Reg 4 = 0x00
Reg 5 = 0x0B
Reg 6 = 0x08
Reg 7 = 0x0E
Reg 8 = 0x0D
Reg 9 = 0x00
Reg A = 0x0F
Reg B = 0x00
Reg C = 0x00
Reg D = 0x00
Reg E = 0x00
Reg F = 0x00
Reg 10 = 0x00
Reg 11 = 0x34
Reg 12 = 0x30
Reg 13 = 0x30
Reg 14 = 0x30
Reg 15 = 0x02
Reg 16 = 0x00
Reg 17 = 0x03
Reg 18 = 0x01
Reg 19 = 0xFF
Reg 1A = 0x00
Reg 1B = 0x01
Reg 1C = 0x10
Reg 1D = 0x00
Reg 1E = 0x00
Reg 1F = 0x00
Reg 20 = 0x1F
Reg 21 = 0x08
Reg 22 = 0x05
Reg 23 = 0x06
Reg 24 = 0x00
Reg 25 = 0x01
Reg 26 = 0x00
Reg 27 = 0x1F
Reg 28 = 0x08
Reg 29 = 0x00
Reg 2A = 0x2C
Reg 2B = 0x06
Reg 2C = 0x40
Reg 2D = 0x08
Reg 2E = 0x00
Reg 2F = 0x02
Reg 30 = 0x0C
Reg 31 = 0x00
Reg 32 = 0x03
Reg 33 = 0x05
Reg 34 = 0x20
Reg 35 = 0x08
Reg 36 = 0x4B
Reg 37 = 0x02
Reg 38 = 0x00
Reg 39 = 0x16
Reg 3A = 0x49
Reg 3B = 0x00
Reg 3C = 0x01
Reg 3D = 0x0A
Reg 3E = 0x50
Reg 3F = 0x04
Reg 40 = 0x65
Reg 41 = 0x00
Reg 42 = 0x01
Reg 43 = 0x08
Reg 44 = 0x98
Reg 45 = 0x04
Reg 46 = 0x65
Reg 47 = 0x00
Reg 48 = 0x01
Reg 49 = 0x01
Reg 4A = 0x0B
Reg 4B = 0x00
Reg 4C = 0x00
Reg 4D = 0x00
Reg 4E = 0x00
Reg 4F = 0x00
Reg 50 = 0x00
Reg 51 = 0x03
Reg 52 = 0x20
Reg 53 = 0x00
Reg 54 = 0xA3
Reg 55 = 0x00
Reg 56 = 0x2C
Reg 57 = 0x06
Reg 58 = 0x40
Reg 59 = 0x08
Reg 5A = 0x00
Reg 5B = 0x01
Reg 5C = 0x01

Reg 5D = 0x08

Am I missing something ? Are there anything I should try to do ?

Regards,

Nobu Furihata

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LMH1983 User Defined Format to Genlock