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DP83867IR, DP83867CR - RGMII mode

Hirotaka Matsumoto
Guru 27585 points
Other Parts Discussed in Thread: DP83867CR, DP83867IR

Hi all

Would you mind if we ask DP83867IR or  DP83867CR?

<Question1>
When 25MHz clock inserts to XI with RGMII mode,  how much of CLK_OUT output? 25MHz or 125MHz? 
Is CLK_OUT possible to output 125MHz always?? 
In case of 1000Base, GTX_CLK needs 125MHz input.
What is the best way to make 125MHz clock input for GTX_CLK?(is it usual to make 125MHz using PLL of FPGA, isn't it?)

<Question2>
The datasheet shows as followings about power sequence;
When operating in 3 supply mode, the 2.5-V VDDA2P5 can come up with or after the 1.8-V VDDA1P8 but not before it.
It is highly recommended that the 1.8-V VDDA1P8 supplies be powered first.
There is no sequencing requirement for other supplies when operating in 3 supply mode.
Is it possible to power on in the order of 1.8V -> 1.0V-> 2.5V?
Should we power on 1.8V or 2.5 -> 1.0V?

<Question3>
When XI connects to 25MHz crystal, the input XI voltage level is the same as VDDIO, right?
If our recognition uncorrect, please let us know?

Kind regards,

Hirotaka Matsumoto

  • 0
    Guru 27585 points

    Hi team

    We guess that your team is so busy, however could you let us know?
    We appreciate for your help always.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 19780 points
    Hello Hirotaka,

    I apologize for the delay.

    Question 1:
    The CLK_OUT is a buffered version of XI. This means that CLK_OUT will output the 25MHz XI frequency.
    For RGMII, GTX_CLK in 1000base will be provided by the connected MAC (could be FPGA, microcontroller, microprocessor). RGMII requires source synchronous data and clock, so using a clock not from the data source (MAC) is not recommended!

    Question 2:
    Yes, you may power 1.8V -> 1.0 -> 2.5V OR 1.8V -> 2.5V -> 1.0V
    Do you have any devices on the 2.5V rail other than DP83867? Is the 2.5V supply dedicated to DP83867?

    Question 3:
    You are correct, XI/XO pins are at the same level as VDDIO.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Guru 27585 points

    Rob san

    Thank you for your reply!
    Do you have any devices on the 2.5V rail other than DP83867? Is the 2.5V supply dedicated to DP83867?
    ->Yes, we guess that 2.5V supply is dedicated to DP83867.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    Guru 27585 points

    Rob san

    We'd like to confirm about <Question1>.

    The datasheet shows as followings;
    Using the I/O Configuration register (address 0x0170), the DP83867 can be configured to output these internal clocks via the CLK_OUT pin.
    By default, the output clock is synchronous to the X_I oscillator / crystal input.
    The default output clock is suitable for use as the reference clock of another DP83867 device.
    Via registers, the output clock can be configured to be synchronous to the receive data at the 125-MHz data rate or at the divide by 5 rate of 25 MHz.

    We quess that CLK_OUT is possible to output 125MHz with synchronous to the receive data register using (address 0x0170).
    So, in this case, because of synchronous to the receive data, it is not impossible to use GTX_CLK, is it?
    What is this CLK_OUT used for?

    We appreciate for your help always.

    Kind regards,

    Hirotaka Matsumoto

  • 0 in reply to Hirotaka Matsumoto
    TI__Mastermind 19780 points

    Hirotaka-san,

    You are correct that the CLK_OUT pin can be configured to output receive and transmit clock of the cable drivers using register 0x170.  The receive clock is synchronous to received data on the Ethernet cable.  It is NOT synchronous to data on the RGMII interface which GTX_CLK is part of.  GTX_CLK, and the driver receive clock are in different domains and are NOT synchronous.

    CLK_OUT is used to provide a reference clock to a second PHY (in synchronous to XI mode).  In transmit clock or receive clock mode, CLK_OUT can be used for some IEEE 802.3 compliance testing. 

    In a standard RGMII interface application, GTX_CLK will be provided by external FPGA/uController along with TXD[3:0] and TX_CTL.

    You can review the RGMII standard here: 

    Best Regards,

  • 0 in reply to Rob Rodrigues
    Guru 27585 points

    Rob san

    Thank you for your reply!
    We got it.

    Kind regards,

    Hirotaka Matsutmoto