ds250DF410 Eval Board PRBS Generator

For the channel in question do you still observe the problem if you disable PRBS checker before enabling PRBS generator?

Thw PRBS generator output data is syncrhonous with input data. If input data is 25.78125Gbps or subrate of it (half-rate or quarter-rate) then output data rate for full rate should be 25.78125Gbps +/- 100ppm.

 25MHz calibration clock is indeed required for normaloperaiton. The evaluation board has crystal oscillator implemented on it to serve a calibration clock reference for the retimer. The default evaluation board confiugration is for the 25MHz oscillator to be connected to the retimer cal_clk_in.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Hi Rodrigo,
Thank you for your help.

First: I can't get PRBS output on any channel.
Next: It appears that the default board configuration is PRBS checker off - so I typically do not disable the PRBS checker since it is already off before trying to turn on the PRBS generator. I have tried turning the PRBS checker on or off and it seems to have no effect on PRBS generator.

So to try to enable PRBS, I do ONLY 2 steps: 1 set CDR select to PRBS generator output and 2 enable PRBS on PRBS Gen/checker page, everything else left at default.
Is turning on the PRBS generator really just a 2 step process, - am I missing anything?

Thanks for the update on the 25MHz clock - nothing happened when I connected up a 25Mhz clock to the board or when I disconnected it. I was confused by the lack of effect!

Any other suggestions on getting the PRBS generator running?

Thanks for your help.

John French

Hi John,

Just so that we are on the same page, can you describe your hardware setup?

For the DUT channel that you are trying to enable PRBS generation for, is there valid 25G data (or 25G sub-rate) present? Is the channel indicating that there is CDR lock?

Regards,

Rodrigo Natal

DPS Applications Engineer

Hi Rodrigo,

Thank you for your help. 

I have a very simple setup:  25G electrical traffic source into TI DS250DF410 Eval board channel 0 differentially, signal detect good, clock lock good: and output of channel 0 going to 50 Termination and other chan 0 output to scope input.  I see a clean eye.  (Scope triggered on initial 25G traffic source clock output).  If I turn on PRBS checker - it shows no errors.  < only did this once and then turned off.

In the Eval board software, I switch 'post lock' select on CDR page to PRBS generator and then enable PRBS on the Gen/Checker page. 

When I switch CDR output to PRBS, my previous nice ~400mV eye disappears and I see about 40mV of noise or clock or unsynchronized data - don't know - doesn't really look like noise - very solid rails - but not synchronous with input and very low level.(of course I do not change output voltage settings !)

IF I leave CDR output at "retimed data" and just enable the PRBS generator, I see a jump in phase, but all else the same, nice eye just delayed relative to original eye.

In order to speed up this debugging process, would it be good to talk live, while I am in front of the setup?  If so pick a time, I am available most of the day tomorrow.

Thank you,

John French

One more question, are you using SigCon Architect GUI software? With SigCon Architect GUI it really should be as simple as clicking on a single button on the PRBS page to enable the generator. You shouldn't be using/setting the post lock selection on CDR page for this. Please try again while skipping that GUI step and see if it works. it should work as we use that configuration very often.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Yes SigCon Architect gui software -
OK so just enable generator and I don't have to touch the CDR select? It will automatically switch the output from retimed data to PRBS?

Yep. The GUI should do the necessary writes for you.

One more question: once I switch to PRBS data out, then I no longer need any data input - Correct?
I assume I can also start PRBS output without any input signal for the CDR to lock to? Also Correct?

The CDR and signal detect will be false and the output will no longer be sync'd with the input as there will be no input.
Do I have to change anything when the CDR is unlocked and signal detect is de-asserted?

When would I use the CDR pre and post lock select options?

Not correct. You do need some input data present for CDR to lock. That input signal could be either 25GE PRBS data, or a clock signal at a sub-rate of 25GE rate. The TI retimer is intended to be a mid-channel device. Moreover it implements a reference-less architecture, and thus relies on input data for clock recovery.

oh .....I see. If I wanted to generate traffic as a system test, I would have to get it some type of clock for it to lock to.
The clock I need could be at any of the sub-rates the datasheet shows the CDR locking, but it definitely needs something.
Thank you for clarifying.

I see,  thank you for clarifying. 

To get a 25.78PRBS, I would need to provide a 25.78G clock input - can I supply a lower subrate to get 25.78 PRBS?

IF there is a clock signal input at a sub-rate of 25GE, and the CDR locks, will the PRBS generator always output only 25G PRBS?

OR will it output PRBS at exactly the rate the CDR is locked to.  ie if I put in 10.3125, will it ONLY generate a 10.3 PRBS or can dividers be setup to produce a 25.78PRBS.

As you can see, my goal is to get a 25.78G PRBS, in the easiest way, in the state of input data loss, if there is another way - please suggest it!

Thanks for your help.

John French

Hi John,

You can indeed provide an input clock signal at sub-rate of 25.78125G and still get 25.78125Gbps PRBS pattern out. Unless you force a lower divider setting on the retimer, the PRBS generator output will always be 25.78125G. For the input clock signal you should be able to go as low as divide by 16  (or 805.66406 MHz.)

Regards,

Rodrigo Natal

Hi Rodrigo,

Thank you for your help - I have the PRBS generator working now with sub-rates and full rates - works great - Thank you.

Unfortunately, I seem to have another problem:  When I load a user pattern in the SigCon GUI and then enable the PRBS generator, I see a different pattern than I expect, I always see about 15 0s and a single 1, regardless of what pattern I enter in the custom pattern entry window.

If I check 0x7c and 0x97, where the custom pattern is to be stored, I indeed see a single 1 bit and the rest 0s. 0x7c =1 and 0x97 =0.  these values remain the same regardless of what I enter in the GUI.

If I try to change these bytes, I cannot - the GUI says they are 'R' not R/W although sometimes I can actually write to 0x7c, but nothing changes when I enable the custom pattern - always one 1 and rest 0s.

Do you have any suggestions to resolve this issue?   It is a GUI bug and if my software were to write to the pattern storage bytes, all would work ok?

Thanks again for all your help.

John French

Hi John, thanks for raising this item related to GUI custom pattern implementation. I will need to look into it. I will get back to you next week on it.

Cordially,

Rodrigo Natal

DPS Applications Engineer

Hi John. there does appear to be a bu with custom pattern in PRBS page. But you should be able to write the desired values in the Low-level page, even when some of the bits are reserved. What you do is select the channel register on the channel in question, enter the hex data you wish to write on the write data field, and then set the mask to 0xFF.

Regards,

Rodrigo