This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Link aggregation with DS32ELX0421 and DS32ELX0124 using 10 LVDS lanes.

Other Parts Discussed in Thread: DS32ELX0421, DS32ELX0124

Hi there, 

I was presented with the idea of link aggregation using 10 lanes LVDS with two sets of DS32ELx# SeDes and a 6 or 7 series xilinx FPGA on both sides. 

I was reading AN-1887 Expanding the Payload With TI's FPGA-Link DS32ELX0421 and DS32ELX0124 Serializer and Deserializer, which uses 4 lanes for data and 5th lane for synchronization. 

I was told to synchronize the 10 deserialized LVDS lanes inside the FPGA. And I am studying the feasibility of that because it seems to be different from approach used in the application notes. 

Thank you for your ideas & suggestions. 

  • Hi Xu,

    Please follow AN-1887 guidelines. AN-1887 first achieves synchronization by using remote sense/back channel and then allows FPGAs to synchronize on the data payload. Also, I would appreciate if you could please tell us about this project or application and your timeline.

  • We need to transport 5.76Gbps payload error free over a 5~10 meter range using low cost cables for medical or industrual applications, assume physical size of a compact flash card + RJ45. 

    We are given 1 week for feasibility and 2~3 months for product. AN-1887 gives a payload of 5Gbps only. 

    Are there any off the sheld products TI or TI's vendor/partners offer? We are not limited to DS32ELX0421 series and solution oriented. 

  • Another question, on how to use the transmitter.
    The application transports video, which contains frames, hsync and vsync etc. In order to maximize throughput we intend to use a buffer in the FPGA, embed hsync/vsync in the frame & line headers and transmit @ 312.5MHz (or our system clock rate) DDR continuously without any gap between the frames & lines.

    I noticed the link transmits training patterns every 200us. What should my FPGA do to take care of the training period to avoid overflow in the serializer?
  • Hi Kelvin,

    As you noted, DS32ELX0421/0124 link aggregation is limited to 5 Gbps data payload. Your application requires 5.76 Gbps data payload. If indeed this is a requirement, then we may have to think of another device set. Would it be possible if you could send us a block diagram of the overall solution so we can better understand how to meet your requirements? If you prefer, you can send me emails at 

    Once remote sense is enabled and we are in link aggregation mode, FPGAs monitor lock indicators and drive or monitor data valid line(TX4). These are the only requirements on the FPGA sides.  If there is a disconnect between the transmitter and receiver then lock indicators become inactive and FPGAs have to go through training again(for example driving data valid line).