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disabling sn65dp159 TMDS ouput automatically during acquisition

Timothy Starr
Expert 2445 points

Hello-

in section 8.4.1 of the data sheet it states: 

During the clock frequency detection period and the retimer acquisition period (that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.

How is this accomplished? We see how to manually turn off the TMDS output using register 0x20h, but not how to automatically. Thanks and Best Regards,

-Tim Starr on behalf of JA@SS

  • 0
    TI__Guru 60870 points
    Hi Tim,

    The design team confirmed that the silicon will not enable the TX signals until PLL lock has occurred. There may be up to a few us of invalid data while the bias is stabilizing, but nothing in the ms range. The 7-ms statement is incorrect and will be removed from the datasheet.

    Regards,
    JMMN
  • 0 in reply to JMMN
    Expert 2445 points

    HI JMMN-

    Your answered directly contradicted the answer I got just before that, from Elias Villegas M. Could you please resolve this conflict for me?

    Is there any way for the host system to tell if the device is locked or not?

    Thanks and Best Regards,

    -Tim

  • 0 in reply to Timothy Starr
    TI__Guru* 76130 points
    I was trying to help with what I know, but JMMN has more bandwidth on this topic, please discard my response.
    Regards
  • 0
    Expert 2445 points
    Hi Elias Villegas M,

    The post from JMMN directly contradicted your statement (see below). Please resolve for me the correct answer between you two, assuming you both work for TI. Thanks, and Best Regards,

    -Tim
  • 0 in reply to Timothy Starr
    TI__Guru 60870 points

    Tim,

    Did this get clarified?

    To summarize:

    The statement below is incorrect and the device will only have several us of invalid clock / data during bias stabilization.  If this is still a concern, you can manually disable TMDS, keep polling for PLL lock and then manually enable TMDS after a delay.

    During the clock frequency detection period and the retimer acquisition period (that last approximately 7-ms), the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.

    Regards,

    JMMN