In our application we are using LMH1981 to drive LMH1983 in auto format detect mode. We are using free-run mode on LOR, and we are trying to maintain a smooth phase (minimal clock disturbance) when returning to Genlock mode. This reference is a black burst signal connected to the LMH1981.
it seems that whenever Genlock mode is engaged from Free-Run mode, the PFD response in the PLL1 controller gives a large deviation and pulls the frequency significantly. This is seen both when reference is asserted via LMH1981 connection or when engaging Genlock mode via register control. Adjusting loop filter bandwidth did not seem to prevent this effect.
I have attached a quick plot of the VCXO control voltage swing when switching from Free-Run to Genlock via register control. HSYNC is present at all times and stable (although hard to see in this plot).
Can we eliminate this deviation, and gently pull the oscillator from the Free-Run reference when engaging Genlock mode?
