DP83848IVV - Hardware Reset Question

Manoj,

Could you provide a register dump after the PHY completes reset? There are conditions where TX_CLK will not toggle as part of normal operation. It is possible that the PHY is being strapped into one of these operational modes.

Please read each register twice and provide the results of both reads. Some register bits latch their status and therefore require two reads to get the current status.

Patrick

Hello Patrick,

We just have a FPGA in this custom board, and haven't enabled any PHY read yet. Would it be easier for you, if I send you the PHY portion of the schematic?, to see the strap options?

Please see the attached image.

Thanks,

Manoj

Manoj,

I don't see any issues with the straps as you have them implemented. My concern is that the FPGA may be pulling or driving pins while the PHY is in reset and thereby causing it to strap into an unintended configuration.

As a quick test, could you probe the test point for the CLK_OUT pin? I am not sure when the PHY reset is asserted relative to power up. If possible, it would be good to probe CLK_OUT after power up (while TX_CLK is driving a 25MHz clock) and after reset (when TX_CLK is no longer toggling).

Patrick

Thanks for your reply Patrick.
We probed the clk_out pin and TX_CLK. After power up both TX_CLK and CLK_OUT pin is pumping out 25MHZ clock.. But after reset, only CLK_OUT pin is working, TX_CLK pin is dead low. So which pins do you think FPGA might be driving when PHY is at reset which might make the PHY to enter unintended configuration?..

Also, one other question. The datasheet talks about three different modes, mode 1, mode 2 and mode3. But I couldn't find info regarding what these modes signifies?. How do we know which mode we have configured our PHY?

Thanks,
Manoj

Manoj,

What frequency do you measure on CLK_OUT before and after reset? Does the frequency change?

Mode 1, mode 2, and mode 3 refer to the LED configuration. For more information, please see the LED Mode Selection table and the description of the LED_CNFG bits in the PHYCR register (address 0x19).

Patrick

Hello Patrick,
The frequency remains the same in both the cases at 25MHZ.

Manoj

Hello Patrick,

Any thoughts on how to debug this moving forward?

Thanks,

Manoj

Manoj,

I had a theory, but it was based on the supposition that the CLK_OUT frequency was changing after reset. Since that is not the case, I am digging a little deeper into the design.

You mentioned that you do not yet have the ability to read registers using the FPGA. Do you have a way to isolate the MDC/MDIO pins of the PHY? For example, are there series resistors on the traces that could be depopulated? If you can separate the MDC/MDIO pins of the PHY, we can suggest an alternate means of reading the registers.

Patrick

Patrick,

Yes the CLK_OUT frequency remains the same. 

We have lifted the MDC and MDIO pin from the board. So, as of now those two pins are isolated. Please let us know how to go about reading the registers.

Thanks,

Manoj

Manoj,

We have a software tool, USB-2-MDIO, that can be used with an inexpensive MSP430 LaunchPad EVM to read the registers. The GUI is available at:
www.ti.com/.../usb-2-mdio

Links to the MSP430 LaunchPad EVM are also available on this page.

Patrick

Manoj,

I have another question. What is the source of the ETH_PWR signal? What is the state of this signal before and after reset is applied? If the PHY is held in power down mode, TX_CLK will stop toggling.

Patrick

Manoj,

I wanted to cycle back to see how you are progressing. Is anything else needed here?

Patrick