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SNx5DP159/TMDS171/TMDS181 EyeScan control register

Igor Uspensky
Intellectual 670 points

Hi,

Glad to see the data sheets recently updated. Still, there are some things which does not seem clear enough. In particular:

Each the part implements the Rx Pattern Verifier Control/Status register. The register has PV_LD[3:0] field which is defined as follows:

PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted high, the
PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are enabled into the
corresponding RX lane. These values are then latched and held when PV_LD[n] is
subsequently deasserted low. 1 bit per lane.

Please clarify what's the PV_TO field mentioned

---

regards,

    Igor

  • 0
    Intellectual 670 points

    I suspect there is no PV_TO field. It seems the whole text is derived from the description for corresponding field of the Pattern Generator Control register (PG_LD[3:0]). Indeed there is PG_TO bit. As for the PV control register, looks like the respective bit is merged to the PV_SEL[24:0] field ("1xx - Timing only mode with sync pulse spacing defined by PV_LEN"). By the way PV_SEL[2:0] would be the better name for the field, I think.

    Any comment?

    BTW one said careless documentation frequently linked to careless implementation. No wonder there is the bug in silicon.

    ---
    regards,
    Igor

  • 0 in reply to Igor Uspensky
    TI__Mastermind 23815 points
    Hi Igor,

    You are right, PV_TO is a typo, this field doesn't exist.

    Regards