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Multi drop interfacing design

Other Parts Discussed in Thread: SN65LVDT41, SN65LVDT14


I need to interfacing different ICs of different PCB cards to the CPU card using SPI bus, which increases distance between master CPU and slave ICs. Therefore I want use LVDS for long distance communication with multi-drop topology using LVDS IC SN65LVDT14 and SN65LVDT41.
 Is it possible to design multi -drop topology using this LVDS SN65LVDT41 IC? Please suggest any circuit  design idea.



  • Hi Swaminath,
    I understand SPI interface is used between master and slave in a point-to-point applications. For multiple slave devices, typically they are daisy chained.
    It is not clear to me how you plan to use multi-drop from/to many slave ICs, can you clarify?
    TK Chin
  • Hi Swaminath,

    Since you are interfacing a CPU and multiple cards I will assume there are several SPI slave devices attached to this bus.  SPI operates at very low speeds, I would be surprised if any additional LVDS buffering was required even over many feet of signal trace length.  Also, SPI uses bi-directional communication on the SCL and SDA connections.  It would be difficult to control this directional signaling with the LVDS transceivers.