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Question of TPD2E2U06-Q1

Other Parts Discussed in Thread: TPD2E2U06-Q1, TPS2546-Q1, TPD2E2U06

Dear Support team

Hello, I have two question about TPD2E2U06-Q1 

◆Question

(1) My customer try to use TPD2E2U06-Q1 in the board of the customer,but the USB IC(TPS2546-Q1) behind breaks down in serge of 25kV.

When I added TPD2E2U06 in parallel one more, USB IC did not break.Could you recommend this how to use? (Please see attached file)

(2) Could you give advice about pattern layout?

Regards

Tomohiro Nagasawa

Question of TPD2E2U06.xlsx

  • Hello Nagasawa-san,

    Let me move this to the ESD forum, they should be able to answer your question.

    Regards,
    Karl
  • Hello

    Your immediate response is highly appreciated.

    Regards

    Tomohiro Nagasawa

  • Hello,

    At 25-kV ESD, the 30-ns peak current will be 50 A. The voltage presented to the protected IC, VESD, will be a function of the breakdown voltage and RDYN of the TVS during the ESD event: VESD = Vbr_TVS + IESDRDYN(TVS). This equation does not consider how the layout can impact VESD. With IESD = 50 A, RDYN(TVS)= 0.5 Ω, Vbr_TVS= 7.5 V, VESD= 32.5 V, which is presented to the protected IC during a 25-kV ESD event. Using two TPD2E2U06-Q1s lowers the VESD to 20 V due to cutting the effective RDYN in half. This 12.5-V difference is likely the solution to successfully pass ESD tests at levels as high as ±25-kV ESD.

    The drawing in the spreadsheet does not really show how close the TVS is to the ESD source, this is important so that any EMI related to the high di/dt on the traces can be minimized. The TVS appear to have good grounds. For very detailed instructions related to ESD Protection Layout on PCB, please see the application note: ESD Protection Layout Guide. If there are still any questions, I look forward to your response.

    Regards,

  • Hello Guy-san

    I appreciate your detailed answer !

    If there are any question, I'll send mail you.

    Regards

    Tomohiro Nagasawa