DS90CR287 - Output jitter

Ryuji

Guru 20090 points

Hello,

There is the TxCLK IN Cycle-to-Cycle Jitter as 2ns in the datasheet.
Could you please let me know the output jitter ?
If the output jitter is varied by difference input jitter, please let me know the correlation.(for example, Figure of input jitter vs. output jitter)

Best Regards,
Ryuji Asaka

over 9 years ago

0 Nasser Mohammadi over 9 years ago

TI__Guru* 93670 points

Greetings Ryuji,

This parameter, TxCLKIN Cycle-toCycle = 2nS, indicates in order to meet TPPOS switching parameters noted in the data sheet maximum clock in jitter must be less than 2nS. Else TPPOS timing parameters could be violated.

Regards,,nasser

0 Michael Lu (Santa Clara) over 9 years ago in reply to Nasser Mohammadi

TI__Mastermind 29655 points

Hi Asaka-san,

To add to Nasser's feedback, I do not expect there to be a correlation between input jitter and output jitter as long as TxCLKIN Cycle-to-Cycle jitter is within specifications, as the Tx device uses an internal PLL to clock in all the parallel inputs and output the LVDS clock.

Regards,

Michael

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DS90CR287 - Output jitter