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SN65DSI84 LVDS output

NAOKI AOYAMA
Guru 11215 points
Other Parts Discussed in Thread: SN65DSI84

Hello,

Our customer uses the SN65DSI84, has some questions about LVDS output condition.

1) How about the LVDS output when there is no DSI data and there is only DSI clock?

2) How about the LVDS output when the IRQ events?

3) Is there any step to disable the LVDS output except for the EN function?

Best Regards,

Naoki Aoyama

  • 0
    TI__Mastermind 18655 points

    Hello Naoki,

    LVDS CLK/data lanes stay low until they are configured to be enabled in corresponding CSR and they will output valid CLK and data after internal PLL locks.

    When SN65DSI84 is in reset state, by setting the EN terminal, the DSI inputs are disabled and outputs are high impedance. 

    LVDS_LINK_CFG will disable only the Channel B output. When the LVDS outputs are disabled they are tied to an 1kOhm pull-down.

    Regards

  • 0 in reply to Joel Jimenez0
    Guru 11215 points
    Hello Joel,

    Thank you for your reply.
    I'll feedback the customer the information.

    Thanks,
    Naoki Aoyama