SN65DSI84 Jitter Constraint Condition for DSI_CLK

Sadanori Kato

Other Parts Discussed in Thread: SN65DSI84

Hi,

Does SN65DSI84 have the jitter constraint condition such as an external reference clock if using the DSI channel A clock instead of an external reference clock to reduce the system costs ?
Could you please give us your advice about that if yes ?

Best regards,
Kato

over 9 years ago

0 Joel Jimenez0 over 9 years ago

TI__Mastermind 18655 points

Hello Kato,

The DSI clock input signal requirement is bounded by input signal amplitude and setup/hold time. As long as they are met, it should be fine. To meet these requirements, the input tr & tf cannot be too slow. In general, the faster the better for input tr&tf .

Regards

0 Sadanori Kato over 9 years ago in reply to Joel Jimenez0

Guru 36540 points

Hi Joel-san,

Thank you for your quick response.
I understood and will contact you if I obtain any questions from our customer.

Best regards,
Kato

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SN65DSI84 Jitter Constraint Condition for DSI_CLK