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TLK2541 - RX_CLK output at link down

Kawai
Guru 19785 points

Hello Team,

Please allow me to ask you about TLK2541.

I am understanding RX_CLK is a recovery clock output.

[Q1]
When link is down, does this RX_CLK recovery clock stops or is RX_CLK output is switched to REFCLK ?

[Q2]
If switching does the RX_CLK have a glitch ?

Best Regards,

Kawai

  • 0
    TI__Genius 16150 points
    Hi Kawai,

    Since the RX_CLK is synchronized to RXD[0:19], if the link is down according to the block diagram, RX_CLK signal would come from the recovered clock of LCKREFN.
    I need to verify with the team for your second question, ASAP I will be back with the answer.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Guru 19785 points
    Hello Luis-san,

    Thank you for your reply.
    Could you please allow me to confirm my understanding?

    Do you mean RX_CLK output would be the following ?
    Link Up : Recovered clock from RXP/RXN clock
    Link Down : Recovered clock from REFCLK

    Please let us know the about Q2 when you have an update.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    Guru 19785 points
    Hello Luis-san,

    We need your help on this questions, Q1 and Q2.

    Please allow me to ask again the output state of RX_CLK when there is no data input at RXP/RXN (Link down).

    Which of the followings does TLK2541 RX_CLK will output when Link is down and when LCKREFN set to High (CDR Enable) ?

    　A). No output - High Impedance ?
    　B). REFCLK - * When link is down, RX_CLK is slowly changing to REFCLK
    　C). REFCLK - * RX_CLK will jump to REFCLK right after the link is down.

    Best Regards,
    Kawai
  • 0 in reply to Kawai
    TI__Expert 5455 points
    Hello Kawai

    The output of the RX_CLK will toggle without an input, but since the CDR will be trying to lock onto the noise at the input the output clock may end up being erratic. It may not end up being a fixed frequency. It could moved around a lot in frequency/phase in order to try to lock onto the input. Also remember that LCKREFN in low the tracking circuitry on the CDR circuit is disable and the recovered byte clock will become a buffered version of REFCLK.

    Please, let me know if you have any questions.

    Regards
    Francisco