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65HVD75 glitches when switching off TE

I am using this SN65HVD75DGK chip in a design and find that it generates a 50ns to 300ns low glitch on the R data line about 70ns after TE goes low. The configuration joins /RE with TE and R with D but I have managed to do some surgery on the msop package to tie /RE low but the glitch is still there. I can shorten the glitch by biasing the line but I can't get rid of it. It doesn't change anything much if I have termination or not or totally remove the cable.

BTW, I have floated the D&T lines and pulled them up with 1k and simply pulsed the TE and the same thing happens so it has nothing to do with the MCU etc. If I try to drive the R line for a few hundred nanoseconds after TE goes low I can see the 65HVD75 winning the battle and holding the line low. If I put a 330R resistor in the R line I can override the glitch but it's a kludge. I am operating at 1Mbit at present just for these tests but the glitch is way too long for higher baud rates. Of course I could get around it in software but my logic analyzers don't like it much.

Now this is a serious question and not meant to be critical but do all the TI fail-safe chips that aren't supposed to glitch do this? I can't go trying them all and the msop pack limits what I can use.

Peter

  • Hi Peter,

    To further understand the issue, can you please share the waveform measured at D, R, DE and /RE.

    also can you share the scheamtic/ block diagram showing the microcontroller and HVD75.

    Thanks and Regards

    Tejas

  • This is the basic circuit that I use with a Parallax Propeller MCU which dedicates a core to serial communications and is able to transmit or receive on the same pin. The MCU pins are just GPIO, there is no shared function etc.

    Top trace is the combined R and D line while the bottom trace shows the TE high then low. In this test the I/O to the MCU was left floating and the D line pulled-up with a 1k resistor so as to eliminate any external influence on this pin. Decoupling is not shown but a 104 is placed right next to the chip as well. Width of the pulse can be shorten a little by applying some positive bias to the RS485 line which further indicates that this is a peculiarity with this type of chip.

  • Hi Peter,

    Thanks for the detailed data, can you also provide us waveform on A & B lines during this issue?

    Regards
    Tejas
  • Okay, but how much more do you need to see, this thing is very easy to bench test to verify anyway. Surely TI engineers must be aware of this problem.

    In this test I float the R+D line with TE low so that the 485 chip is driving the D line high, then I drive TE high where we can see the R+D line starting to decay since nothing is driving it (for the test) but still a logic high, then TE low followed by the glitch from the 65HVD75 chip. There is nothing on the bus to indicate that it is contributing to this glitch and in fact I can short the bus or bias the bus and the glitch remains. Probing Vdd on the chip during this period reveals no abnormalities, it is extremely clean.


    I'm in no doubt that this is a problem with the chip and in fact I have searched for this exact same problem and found someone describing this very same thing last year when trying to interface to an ARM chip and the hardware UART would receive garbage because of the glitch.


    I know it is not like any manufacturer to openly acknowledge that they have a problem but there is. I can work-around this or design in the 65HVD485 chips on a 5V rail by adding a simple current limit resistor in the D line which will work too. I use 65HVD3082s in other designs without any problems that I am aware of.

    1: D  2: TE 3,4: Bus

  • Hi Peter,

    Sorry to say that this part is creating glitch.
    Kindly check with HVD 70/71/73/74/76/77,HVD147X that has been fixed for glitch. also you may check HVD1782 that I have bench tested and works fine.


    Regards
    Tejas