This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IS transition time

Hi,

I would like you to confirm whether there is requirement for rising/falling time for each I/O pins.

I understood that there is definition about RGMII/SGMII signals (MAC interface) in datasheet. However, there is no definition about other singals.

Especially, We would like to know whether there is transition requirement for "PWDN" and "RESET_N".

Best Regards,

Machida