SN65DSI84 Skew between FlatLink™ Channel A LVDS Clock Output and Channel B LVDS Clock Output

Sadanori Kato

Hi,

Could you please tell us the skew between FlatLink™ channel A lvds clock output and channel B lvds clock output in the HS mode ?
If this parameter is not defined in the specification, could you please let us know an actual value ?

Best regards,
Kato

over 10 years ago

0 Joel Jimenez0 over 10 years ago

TI__Mastermind 18655 points

Hello Kato,

Theoretically, the CLK distribution should be nearly identical between two LVDS interfaces since both LVDS CLKS are generated from one CLK source so they are the same between two as the datasheet says. The skew is possible due to other mismatches but should not be greater than 10ps.

Regards

0 Sadanori Kato over 10 years ago in reply to Joel Jimenez0

Guru 36540 points

Hi Joel-san,

Thank you for your support and suggestion.
I understood and will contact you if I obtain any questions from our customer.

Best regards,
Kato

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SN65DSI84 Skew between FlatLink™ Channel A LVDS Clock Output and Channel B LVDS Clock Output